1 /*
2 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 *
6 * Authors: Younghwan Joo <yhwan.joo@samsung.com>
7 * Sylwester Nawrocki <s.nawrocki@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #ifndef FIMC_IS_H_
14 #define FIMC_IS_H_
15
16 #include <asm/barrier.h>
17 #include <linux/clk.h>
18 #include <linux/device.h>
19 #include <linux/kernel.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/platform_device.h>
22 #include <linux/sizes.h>
23 #include <linux/spinlock.h>
24 #include <linux/types.h>
25 #include <media/videobuf2-core.h>
26 #include <media/v4l2-ctrls.h>
27
28 #include "fimc-isp.h"
29 #include "fimc-is-command.h"
30 #include "fimc-is-sensor.h"
31 #include "fimc-is-param.h"
32 #include "fimc-is-regs.h"
33
34 #define FIMC_IS_DRV_NAME "exynos4-fimc-is"
35
36 #define FIMC_IS_FW_FILENAME "fimc_is_fw.bin"
37 #define FIMC_IS_SETFILE_6A3 "setfile.bin"
38
39 #define FIMC_IS_FW_LOAD_TIMEOUT 1000 /* ms */
40 #define FIMC_IS_POWER_ON_TIMEOUT 1000 /* us */
41
42 #define FIMC_IS_SENSOR_NUM 2
43
44 /* Memory definitions */
45 #define FIMC_IS_CPU_MEM_SIZE (0xa00000)
46 #define FIMC_IS_CPU_BASE_MASK ((1 << 26) - 1)
47 #define FIMC_IS_REGION_SIZE 0x5000
48
49 #define FIMC_IS_DEBUG_REGION_OFFSET 0x0084b000
50 #define FIMC_IS_SHARED_REGION_OFFSET 0x008c0000
51 #define FIMC_IS_FW_INFO_LEN 31
52 #define FIMC_IS_FW_VER_LEN 7
53 #define FIMC_IS_FW_DESC_LEN (FIMC_IS_FW_INFO_LEN + \
54 FIMC_IS_FW_VER_LEN)
55 #define FIMC_IS_SETFILE_INFO_LEN 39
56
57 #define FIMC_IS_EXTRA_MEM_SIZE (FIMC_IS_EXTRA_FW_SIZE + \
58 FIMC_IS_EXTRA_SETFILE_SIZE + 0x1000)
59 #define FIMC_IS_EXTRA_FW_SIZE 0x180000
60 #define FIMC_IS_EXTRA_SETFILE_SIZE 0x4b000
61
62 /* TODO: revisit */
63 #define FIMC_IS_FW_ADDR_MASK ((1 << 26) - 1)
64 #define FIMC_IS_FW_SIZE_MAX (SZ_4M)
65 #define FIMC_IS_FW_SIZE_MIN (SZ_32K)
66
67 #define ATCLK_MCUISP_FREQUENCY 100000000UL
68 #define ACLK_AXI_FREQUENCY 100000000UL
69
70 enum {
71 ISS_CLK_PPMUISPX,
72 ISS_CLK_PPMUISPMX,
73 ISS_CLK_LITE0,
74 ISS_CLK_LITE1,
75 ISS_CLK_MPLL,
76 ISS_CLK_ISP,
77 ISS_CLK_DRC,
78 ISS_CLK_FD,
79 ISS_CLK_MCUISP,
80 ISS_CLK_UART,
81 ISS_GATE_CLKS_MAX,
82 ISS_CLK_ISP_DIV0 = ISS_GATE_CLKS_MAX,
83 ISS_CLK_ISP_DIV1,
84 ISS_CLK_MCUISP_DIV0,
85 ISS_CLK_MCUISP_DIV1,
86 ISS_CLK_ACLK200,
87 ISS_CLK_ACLK200_DIV,
88 ISS_CLK_ACLK400MCUISP,
89 ISS_CLK_ACLK400MCUISP_DIV,
90 ISS_CLKS_MAX
91 };
92
93 /* The driver's internal state flags */
94 enum {
95 IS_ST_IDLE,
96 IS_ST_PWR_ON,
97 IS_ST_A5_PWR_ON,
98 IS_ST_FW_LOADED,
99 IS_ST_OPEN_SENSOR,
100 IS_ST_SETFILE_LOADED,
101 IS_ST_INIT_DONE,
102 IS_ST_STREAM_ON,
103 IS_ST_STREAM_OFF,
104 IS_ST_CHANGE_MODE,
105 IS_ST_BLOCK_CMD_CLEARED,
106 IS_ST_SET_ZOOM,
107 IS_ST_PWR_SUBIP_ON,
108 IS_ST_END,
109 };
110
111 enum af_state {
112 FIMC_IS_AF_IDLE = 0,
113 FIMC_IS_AF_SETCONFIG = 1,
114 FIMC_IS_AF_RUNNING = 2,
115 FIMC_IS_AF_LOCK = 3,
116 FIMC_IS_AF_ABORT = 4,
117 FIMC_IS_AF_FAILED = 5,
118 };
119
120 enum af_lock_state {
121 FIMC_IS_AF_UNLOCKED = 0,
122 FIMC_IS_AF_LOCKED = 2
123 };
124
125 enum ae_lock_state {
126 FIMC_IS_AE_UNLOCKED = 0,
127 FIMC_IS_AE_LOCKED = 1
128 };
129
130 enum awb_lock_state {
131 FIMC_IS_AWB_UNLOCKED = 0,
132 FIMC_IS_AWB_LOCKED = 1
133 };
134
135 enum {
136 IS_METERING_CONFIG_CMD,
137 IS_METERING_CONFIG_WIN_POS_X,
138 IS_METERING_CONFIG_WIN_POS_Y,
139 IS_METERING_CONFIG_WIN_WIDTH,
140 IS_METERING_CONFIG_WIN_HEIGHT,
141 IS_METERING_CONFIG_MAX
142 };
143
144 struct is_setfile {
145 const struct firmware *info;
146 int state;
147 u32 sub_index;
148 u32 base;
149 size_t size;
150 };
151
152 struct is_fd_result_header {
153 u32 offset;
154 u32 count;
155 u32 index;
156 u32 curr_index;
157 u32 width;
158 u32 height;
159 };
160
161 struct is_af_info {
162 u16 mode;
163 u32 af_state;
164 u32 af_lock_state;
165 u32 ae_lock_state;
166 u32 awb_lock_state;
167 u16 pos_x;
168 u16 pos_y;
169 u16 prev_pos_x;
170 u16 prev_pos_y;
171 u16 use_af;
172 };
173
174 struct fimc_is_firmware {
175 const struct firmware *f_w;
176
177 dma_addr_t paddr;
178 void *vaddr;
179 unsigned int size;
180
181 char info[FIMC_IS_FW_INFO_LEN + 1];
182 char version[FIMC_IS_FW_VER_LEN + 1];
183 char setfile_info[FIMC_IS_SETFILE_INFO_LEN + 1];
184 u8 state;
185 };
186
187 struct fimc_is_memory {
188 /* physical base address */
189 dma_addr_t paddr;
190 /* virtual base address */
191 void *vaddr;
192 /* total length */
193 unsigned int size;
194 };
195
196 #define FIMC_IS_I2H_MAX_ARGS 12
197
198 struct i2h_cmd {
199 u32 cmd;
200 u32 sensor_id;
201 u16 num_args;
202 u32 args[FIMC_IS_I2H_MAX_ARGS];
203 };
204
205 struct h2i_cmd {
206 u16 cmd_type;
207 u32 entry_id;
208 };
209
210 #define FIMC_IS_DEBUG_MSG 0x3f
211 #define FIMC_IS_DEBUG_LEVEL 3
212
213 struct fimc_is_setfile {
214 const struct firmware *info;
215 unsigned int state;
216 unsigned int size;
217 u32 sub_index;
218 u32 base;
219 };
220
221 struct chain_config {
222 struct global_param global;
223 struct sensor_param sensor;
224 struct isp_param isp;
225 struct drc_param drc;
226 struct fd_param fd;
227
228 unsigned long p_region_index1;
229 unsigned long p_region_index2;
230 };
231
232 /**
233 * struct fimc_is - fimc-is data structure
234 * @pdev: pointer to FIMC-IS platform device
235 * @pctrl: pointer to pinctrl structure for this device
236 * @v4l2_dev: pointer to top the level v4l2_device
237 * @alloc_ctx: videobuf2 memory allocator context
238 * @lock: mutex serializing video device and the subdev operations
239 * @slock: spinlock protecting this data structure and the hw registers
240 * @clocks: FIMC-LITE gate clock
241 * @regs: MCUCTL mmapped registers region
242 * @pmu_regs: PMU ISP mmapped registers region
243 * @irq_queue: interrupt handling waitqueue
244 * @lpm: low power mode flag
245 * @state: internal driver's state flags
246 */
247 struct fimc_is {
248 struct platform_device *pdev;
249 struct pinctrl *pctrl;
250 struct v4l2_device *v4l2_dev;
251
252 struct fimc_is_firmware fw;
253 struct fimc_is_memory memory;
254 struct firmware *f_w;
255
256 struct fimc_isp isp;
257 struct fimc_is_sensor *sensor;
258 struct fimc_is_setfile setfile;
259
260 struct vb2_alloc_ctx *alloc_ctx;
261 struct v4l2_ctrl_handler ctrl_handler;
262
263 struct mutex lock;
264 spinlock_t slock;
265
266 struct clk *clocks[ISS_CLKS_MAX];
267 void __iomem *regs;
268 void __iomem *pmu_regs;
269 int irq;
270 wait_queue_head_t irq_queue;
271 u8 lpm;
272
273 unsigned long state;
274 unsigned int sensor_index;
275
276 struct i2h_cmd i2h_cmd;
277 struct h2i_cmd h2i_cmd;
278 struct is_fd_result_header fd_header;
279
280 struct chain_config config[IS_SC_MAX];
281 unsigned config_index;
282
283 struct is_region *is_p_region;
284 dma_addr_t is_dma_p_region;
285 struct is_share_region *is_shared_region;
286 struct is_af_info af;
287
288 struct dentry *debugfs_entry;
289 };
290
fimc_isp_to_is(struct fimc_isp * isp)291 static inline struct fimc_is *fimc_isp_to_is(struct fimc_isp *isp)
292 {
293 return container_of(isp, struct fimc_is, isp);
294 }
295
fimc_is_mem_barrier(void)296 static inline void fimc_is_mem_barrier(void)
297 {
298 mb();
299 }
300
fimc_is_set_param_bit(struct fimc_is * is,int num)301 static inline void fimc_is_set_param_bit(struct fimc_is *is, int num)
302 {
303 struct chain_config *cfg = &is->config[is->config_index];
304
305 if (num >= 32)
306 set_bit(num - 32, &cfg->p_region_index2);
307 else
308 set_bit(num, &cfg->p_region_index1);
309 }
310
fimc_is_set_param_ctrl_cmd(struct fimc_is * is,int cmd)311 static inline void fimc_is_set_param_ctrl_cmd(struct fimc_is *is, int cmd)
312 {
313 is->is_p_region->parameter.isp.control.cmd = cmd;
314 }
315
mcuctl_write(u32 v,struct fimc_is * is,unsigned int offset)316 static inline void mcuctl_write(u32 v, struct fimc_is *is, unsigned int offset)
317 {
318 writel(v, is->regs + offset);
319 }
320
mcuctl_read(struct fimc_is * is,unsigned int offset)321 static inline u32 mcuctl_read(struct fimc_is *is, unsigned int offset)
322 {
323 return readl(is->regs + offset);
324 }
325
pmuisp_write(u32 v,struct fimc_is * is,unsigned int offset)326 static inline void pmuisp_write(u32 v, struct fimc_is *is, unsigned int offset)
327 {
328 writel(v, is->pmu_regs + offset);
329 }
330
pmuisp_read(struct fimc_is * is,unsigned int offset)331 static inline u32 pmuisp_read(struct fimc_is *is, unsigned int offset)
332 {
333 return readl(is->pmu_regs + offset);
334 }
335
336 int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
337 unsigned int state, unsigned int timeout);
338 int fimc_is_cpu_set_power(struct fimc_is *is, int on);
339 int fimc_is_start_firmware(struct fimc_is *is);
340 int fimc_is_hw_initialize(struct fimc_is *is);
341 void fimc_is_log_dump(const char *level, const void *buf, size_t len);
342
343 #endif /* FIMC_IS_H_ */
344