1 /* 2 * NAND Flash Controller Device Driver 3 * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 17 * 18 */ 19 20 #include <linux/mtd/nand.h> 21 22 #define DEVICE_RESET 0x0 23 #define DEVICE_RESET__BANK0 0x0001 24 #define DEVICE_RESET__BANK1 0x0002 25 #define DEVICE_RESET__BANK2 0x0004 26 #define DEVICE_RESET__BANK3 0x0008 27 28 #define TRANSFER_SPARE_REG 0x10 29 #define TRANSFER_SPARE_REG__FLAG 0x0001 30 31 #define LOAD_WAIT_CNT 0x20 32 #define LOAD_WAIT_CNT__VALUE 0xffff 33 34 #define PROGRAM_WAIT_CNT 0x30 35 #define PROGRAM_WAIT_CNT__VALUE 0xffff 36 37 #define ERASE_WAIT_CNT 0x40 38 #define ERASE_WAIT_CNT__VALUE 0xffff 39 40 #define INT_MON_CYCCNT 0x50 41 #define INT_MON_CYCCNT__VALUE 0xffff 42 43 #define RB_PIN_ENABLED 0x60 44 #define RB_PIN_ENABLED__BANK0 0x0001 45 #define RB_PIN_ENABLED__BANK1 0x0002 46 #define RB_PIN_ENABLED__BANK2 0x0004 47 #define RB_PIN_ENABLED__BANK3 0x0008 48 49 #define MULTIPLANE_OPERATION 0x70 50 #define MULTIPLANE_OPERATION__FLAG 0x0001 51 52 #define MULTIPLANE_READ_ENABLE 0x80 53 #define MULTIPLANE_READ_ENABLE__FLAG 0x0001 54 55 #define COPYBACK_DISABLE 0x90 56 #define COPYBACK_DISABLE__FLAG 0x0001 57 58 #define CACHE_WRITE_ENABLE 0xa0 59 #define CACHE_WRITE_ENABLE__FLAG 0x0001 60 61 #define CACHE_READ_ENABLE 0xb0 62 #define CACHE_READ_ENABLE__FLAG 0x0001 63 64 #define PREFETCH_MODE 0xc0 65 #define PREFETCH_MODE__PREFETCH_EN 0x0001 66 #define PREFETCH_MODE__PREFETCH_BURST_LENGTH 0xfff0 67 68 #define CHIP_ENABLE_DONT_CARE 0xd0 69 #define CHIP_EN_DONT_CARE__FLAG 0x01 70 71 #define ECC_ENABLE 0xe0 72 #define ECC_ENABLE__FLAG 0x0001 73 74 #define GLOBAL_INT_ENABLE 0xf0 75 #define GLOBAL_INT_EN_FLAG 0x01 76 77 #define WE_2_RE 0x100 78 #define WE_2_RE__VALUE 0x003f 79 80 #define ADDR_2_DATA 0x110 81 #define ADDR_2_DATA__VALUE 0x003f 82 83 #define RE_2_WE 0x120 84 #define RE_2_WE__VALUE 0x003f 85 86 #define ACC_CLKS 0x130 87 #define ACC_CLKS__VALUE 0x000f 88 89 #define NUMBER_OF_PLANES 0x140 90 #define NUMBER_OF_PLANES__VALUE 0x0007 91 92 #define PAGES_PER_BLOCK 0x150 93 #define PAGES_PER_BLOCK__VALUE 0xffff 94 95 #define DEVICE_WIDTH 0x160 96 #define DEVICE_WIDTH__VALUE 0x0003 97 98 #define DEVICE_MAIN_AREA_SIZE 0x170 99 #define DEVICE_MAIN_AREA_SIZE__VALUE 0xffff 100 101 #define DEVICE_SPARE_AREA_SIZE 0x180 102 #define DEVICE_SPARE_AREA_SIZE__VALUE 0xffff 103 104 #define TWO_ROW_ADDR_CYCLES 0x190 105 #define TWO_ROW_ADDR_CYCLES__FLAG 0x0001 106 107 #define MULTIPLANE_ADDR_RESTRICT 0x1a0 108 #define MULTIPLANE_ADDR_RESTRICT__FLAG 0x0001 109 110 #define ECC_CORRECTION 0x1b0 111 #define ECC_CORRECTION__VALUE 0x001f 112 113 #define READ_MODE 0x1c0 114 #define READ_MODE__VALUE 0x000f 115 116 #define WRITE_MODE 0x1d0 117 #define WRITE_MODE__VALUE 0x000f 118 119 #define COPYBACK_MODE 0x1e0 120 #define COPYBACK_MODE__VALUE 0x000f 121 122 #define RDWR_EN_LO_CNT 0x1f0 123 #define RDWR_EN_LO_CNT__VALUE 0x001f 124 125 #define RDWR_EN_HI_CNT 0x200 126 #define RDWR_EN_HI_CNT__VALUE 0x001f 127 128 #define MAX_RD_DELAY 0x210 129 #define MAX_RD_DELAY__VALUE 0x000f 130 131 #define CS_SETUP_CNT 0x220 132 #define CS_SETUP_CNT__VALUE 0x001f 133 134 #define SPARE_AREA_SKIP_BYTES 0x230 135 #define SPARE_AREA_SKIP_BYTES__VALUE 0x003f 136 137 #define SPARE_AREA_MARKER 0x240 138 #define SPARE_AREA_MARKER__VALUE 0xffff 139 140 #define DEVICES_CONNECTED 0x250 141 #define DEVICES_CONNECTED__VALUE 0x0007 142 143 #define DIE_MASK 0x260 144 #define DIE_MASK__VALUE 0x00ff 145 146 #define FIRST_BLOCK_OF_NEXT_PLANE 0x270 147 #define FIRST_BLOCK_OF_NEXT_PLANE__VALUE 0xffff 148 149 #define WRITE_PROTECT 0x280 150 #define WRITE_PROTECT__FLAG 0x0001 151 152 #define RE_2_RE 0x290 153 #define RE_2_RE__VALUE 0x003f 154 155 #define MANUFACTURER_ID 0x300 156 #define MANUFACTURER_ID__VALUE 0x00ff 157 158 #define DEVICE_ID 0x310 159 #define DEVICE_ID__VALUE 0x00ff 160 161 #define DEVICE_PARAM_0 0x320 162 #define DEVICE_PARAM_0__VALUE 0x00ff 163 164 #define DEVICE_PARAM_1 0x330 165 #define DEVICE_PARAM_1__VALUE 0x00ff 166 167 #define DEVICE_PARAM_2 0x340 168 #define DEVICE_PARAM_2__VALUE 0x00ff 169 170 #define LOGICAL_PAGE_DATA_SIZE 0x350 171 #define LOGICAL_PAGE_DATA_SIZE__VALUE 0xffff 172 173 #define LOGICAL_PAGE_SPARE_SIZE 0x360 174 #define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff 175 176 #define REVISION 0x370 177 #define REVISION__VALUE 0xffff 178 179 #define ONFI_DEVICE_FEATURES 0x380 180 #define ONFI_DEVICE_FEATURES__VALUE 0x003f 181 182 #define ONFI_OPTIONAL_COMMANDS 0x390 183 #define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f 184 185 #define ONFI_TIMING_MODE 0x3a0 186 #define ONFI_TIMING_MODE__VALUE 0x003f 187 188 #define ONFI_PGM_CACHE_TIMING_MODE 0x3b0 189 #define ONFI_PGM_CACHE_TIMING_MODE__VALUE 0x003f 190 191 #define ONFI_DEVICE_NO_OF_LUNS 0x3c0 192 #define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS 0x00ff 193 #define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE 0x0100 194 195 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0 196 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE 0xffff 197 198 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0 199 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE 0xffff 200 201 #define FEATURES 0x3f0 202 #define FEATURES__N_BANKS 0x0003 203 #define FEATURES__ECC_MAX_ERR 0x003c 204 #define FEATURES__DMA 0x0040 205 #define FEATURES__CMD_DMA 0x0080 206 #define FEATURES__PARTITION 0x0100 207 #define FEATURES__XDMA_SIDEBAND 0x0200 208 #define FEATURES__GPREG 0x0400 209 #define FEATURES__INDEX_ADDR 0x0800 210 211 #define TRANSFER_MODE 0x400 212 #define TRANSFER_MODE__VALUE 0x0003 213 214 #define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50)) 215 #define INTR_EN(__bank) (0x420 + ((__bank) * 0x50)) 216 217 #define INTR_STATUS__ECC_TRANSACTION_DONE 0x0001 218 #define INTR_STATUS__ECC_ERR 0x0002 219 #define INTR_STATUS__DMA_CMD_COMP 0x0004 220 #define INTR_STATUS__TIME_OUT 0x0008 221 #define INTR_STATUS__PROGRAM_FAIL 0x0010 222 #define INTR_STATUS__ERASE_FAIL 0x0020 223 #define INTR_STATUS__LOAD_COMP 0x0040 224 #define INTR_STATUS__PROGRAM_COMP 0x0080 225 #define INTR_STATUS__ERASE_COMP 0x0100 226 #define INTR_STATUS__PIPE_CPYBCK_CMD_COMP 0x0200 227 #define INTR_STATUS__LOCKED_BLK 0x0400 228 #define INTR_STATUS__UNSUP_CMD 0x0800 229 #define INTR_STATUS__INT_ACT 0x1000 230 #define INTR_STATUS__RST_COMP 0x2000 231 #define INTR_STATUS__PIPE_CMD_ERR 0x4000 232 #define INTR_STATUS__PAGE_XFER_INC 0x8000 233 234 #define INTR_EN__ECC_TRANSACTION_DONE 0x0001 235 #define INTR_EN__ECC_ERR 0x0002 236 #define INTR_EN__DMA_CMD_COMP 0x0004 237 #define INTR_EN__TIME_OUT 0x0008 238 #define INTR_EN__PROGRAM_FAIL 0x0010 239 #define INTR_EN__ERASE_FAIL 0x0020 240 #define INTR_EN__LOAD_COMP 0x0040 241 #define INTR_EN__PROGRAM_COMP 0x0080 242 #define INTR_EN__ERASE_COMP 0x0100 243 #define INTR_EN__PIPE_CPYBCK_CMD_COMP 0x0200 244 #define INTR_EN__LOCKED_BLK 0x0400 245 #define INTR_EN__UNSUP_CMD 0x0800 246 #define INTR_EN__INT_ACT 0x1000 247 #define INTR_EN__RST_COMP 0x2000 248 #define INTR_EN__PIPE_CMD_ERR 0x4000 249 #define INTR_EN__PAGE_XFER_INC 0x8000 250 251 #define PAGE_CNT(__bank) (0x430 + ((__bank) * 0x50)) 252 #define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50)) 253 #define ERR_BLOCK_ADDR(__bank) (0x450 + ((__bank) * 0x50)) 254 255 #define DATA_INTR 0x550 256 #define DATA_INTR__WRITE_SPACE_AV 0x0001 257 #define DATA_INTR__READ_DATA_AV 0x0002 258 259 #define DATA_INTR_EN 0x560 260 #define DATA_INTR_EN__WRITE_SPACE_AV 0x0001 261 #define DATA_INTR_EN__READ_DATA_AV 0x0002 262 263 #define GPREG_0 0x570 264 #define GPREG_0__VALUE 0xffff 265 266 #define GPREG_1 0x580 267 #define GPREG_1__VALUE 0xffff 268 269 #define GPREG_2 0x590 270 #define GPREG_2__VALUE 0xffff 271 272 #define GPREG_3 0x5a0 273 #define GPREG_3__VALUE 0xffff 274 275 #define ECC_THRESHOLD 0x600 276 #define ECC_THRESHOLD__VALUE 0x03ff 277 278 #define ECC_ERROR_BLOCK_ADDRESS 0x610 279 #define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff 280 281 #define ECC_ERROR_PAGE_ADDRESS 0x620 282 #define ECC_ERROR_PAGE_ADDRESS__VALUE 0x0fff 283 #define ECC_ERROR_PAGE_ADDRESS__BANK 0xf000 284 285 #define ECC_ERROR_ADDRESS 0x630 286 #define ECC_ERROR_ADDRESS__OFFSET 0x0fff 287 #define ECC_ERROR_ADDRESS__SECTOR_NR 0xf000 288 289 #define ERR_CORRECTION_INFO 0x640 290 #define ERR_CORRECTION_INFO__BYTEMASK 0x00ff 291 #define ERR_CORRECTION_INFO__DEVICE_NR 0x0f00 292 #define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000 293 #define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000 294 295 #define DMA_ENABLE 0x700 296 #define DMA_ENABLE__FLAG 0x0001 297 298 #define IGNORE_ECC_DONE 0x710 299 #define IGNORE_ECC_DONE__FLAG 0x0001 300 301 #define DMA_INTR 0x720 302 #define DMA_INTR__TARGET_ERROR 0x0001 303 #define DMA_INTR__DESC_COMP_CHANNEL0 0x0002 304 #define DMA_INTR__DESC_COMP_CHANNEL1 0x0004 305 #define DMA_INTR__DESC_COMP_CHANNEL2 0x0008 306 #define DMA_INTR__DESC_COMP_CHANNEL3 0x0010 307 #define DMA_INTR__MEMCOPY_DESC_COMP 0x0020 308 309 #define DMA_INTR_EN 0x730 310 #define DMA_INTR_EN__TARGET_ERROR 0x0001 311 #define DMA_INTR_EN__DESC_COMP_CHANNEL0 0x0002 312 #define DMA_INTR_EN__DESC_COMP_CHANNEL1 0x0004 313 #define DMA_INTR_EN__DESC_COMP_CHANNEL2 0x0008 314 #define DMA_INTR_EN__DESC_COMP_CHANNEL3 0x0010 315 #define DMA_INTR_EN__MEMCOPY_DESC_COMP 0x0020 316 317 #define TARGET_ERR_ADDR_LO 0x740 318 #define TARGET_ERR_ADDR_LO__VALUE 0xffff 319 320 #define TARGET_ERR_ADDR_HI 0x750 321 #define TARGET_ERR_ADDR_HI__VALUE 0xffff 322 323 #define CHNL_ACTIVE 0x760 324 #define CHNL_ACTIVE__CHANNEL0 0x0001 325 #define CHNL_ACTIVE__CHANNEL1 0x0002 326 #define CHNL_ACTIVE__CHANNEL2 0x0004 327 #define CHNL_ACTIVE__CHANNEL3 0x0008 328 329 #define ACTIVE_SRC_ID 0x800 330 #define ACTIVE_SRC_ID__VALUE 0x00ff 331 332 #define PTN_INTR 0x810 333 #define PTN_INTR__CONFIG_ERROR 0x0001 334 #define PTN_INTR__ACCESS_ERROR_BANK0 0x0002 335 #define PTN_INTR__ACCESS_ERROR_BANK1 0x0004 336 #define PTN_INTR__ACCESS_ERROR_BANK2 0x0008 337 #define PTN_INTR__ACCESS_ERROR_BANK3 0x0010 338 #define PTN_INTR__REG_ACCESS_ERROR 0x0020 339 340 #define PTN_INTR_EN 0x820 341 #define PTN_INTR_EN__CONFIG_ERROR 0x0001 342 #define PTN_INTR_EN__ACCESS_ERROR_BANK0 0x0002 343 #define PTN_INTR_EN__ACCESS_ERROR_BANK1 0x0004 344 #define PTN_INTR_EN__ACCESS_ERROR_BANK2 0x0008 345 #define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010 346 #define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020 347 348 #define PERM_SRC_ID(__bank) (0x830 + ((__bank) * 0x40)) 349 #define PERM_SRC_ID__SRCID 0x00ff 350 #define PERM_SRC_ID__DIRECT_ACCESS_ACTIVE 0x0800 351 #define PERM_SRC_ID__WRITE_ACTIVE 0x2000 352 #define PERM_SRC_ID__READ_ACTIVE 0x4000 353 #define PERM_SRC_ID__PARTITION_VALID 0x8000 354 355 #define MIN_BLK_ADDR(__bank) (0x840 + ((__bank) * 0x40)) 356 #define MIN_BLK_ADDR__VALUE 0xffff 357 358 #define MAX_BLK_ADDR(__bank) (0x850 + ((__bank) * 0x40)) 359 #define MAX_BLK_ADDR__VALUE 0xffff 360 361 #define MIN_MAX_BANK(__bank) (0x860 + ((__bank) * 0x40)) 362 #define MIN_MAX_BANK__MIN_VALUE 0x0003 363 #define MIN_MAX_BANK__MAX_VALUE 0x000c 364 365 366 /* ffsdefs.h */ 367 #define CLEAR 0 /*use this to clear a field instead of "fail"*/ 368 #define SET 1 /*use this to set a field instead of "pass"*/ 369 #define FAIL 1 /*failed flag*/ 370 #define PASS 0 /*success flag*/ 371 #define ERR -1 /*error flag*/ 372 373 /* lld.h */ 374 #define GOOD_BLOCK 0 375 #define DEFECTIVE_BLOCK 1 376 #define READ_ERROR 2 377 378 #define CLK_X 5 379 #define CLK_MULTI 4 380 381 /* spectraswconfig.h */ 382 #define CMD_DMA 0 383 384 #define SPECTRA_PARTITION_ID 0 385 /**** Block Table and Reserved Block Parameters *****/ 386 #define SPECTRA_START_BLOCK 3 387 #define NUM_FREE_BLOCKS_GATE 30 388 389 /* KBV - Updated to LNW scratch register address */ 390 #define SCRATCH_REG_ADDR CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR 391 #define SCRATCH_REG_SIZE 64 392 393 #define GLOB_HWCTL_DEFAULT_BLKS 2048 394 395 #define SUPPORT_15BITECC 1 396 #define SUPPORT_8BITECC 1 397 398 #define CUSTOM_CONF_PARAMS 0 399 400 #define ONFI_BLOOM_TIME 1 401 #define MODE5_WORKAROUND 0 402 403 /* lld_nand.h */ 404 /* 405 * NAND Flash Controller Device Driver 406 * Copyright (c) 2009, Intel Corporation and its suppliers. 407 * 408 * This program is free software; you can redistribute it and/or modify it 409 * under the terms and conditions of the GNU General Public License, 410 * version 2, as published by the Free Software Foundation. 411 * 412 * This program is distributed in the hope it will be useful, but WITHOUT 413 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 414 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 415 * more details. 416 * 417 * You should have received a copy of the GNU General Public License along with 418 * this program; if not, write to the Free Software Foundation, Inc., 419 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 420 * 421 */ 422 423 #ifndef _LLD_NAND_ 424 #define _LLD_NAND_ 425 426 #define MODE_00 0x00000000 427 #define MODE_01 0x04000000 428 #define MODE_10 0x08000000 429 #define MODE_11 0x0C000000 430 431 432 #define DATA_TRANSFER_MODE 0 433 #define PROTECTION_PER_BLOCK 1 434 #define LOAD_WAIT_COUNT 2 435 #define PROGRAM_WAIT_COUNT 3 436 #define ERASE_WAIT_COUNT 4 437 #define INT_MONITOR_CYCLE_COUNT 5 438 #define READ_BUSY_PIN_ENABLED 6 439 #define MULTIPLANE_OPERATION_SUPPORT 7 440 #define PRE_FETCH_MODE 8 441 #define CE_DONT_CARE_SUPPORT 9 442 #define COPYBACK_SUPPORT 10 443 #define CACHE_WRITE_SUPPORT 11 444 #define CACHE_READ_SUPPORT 12 445 #define NUM_PAGES_IN_BLOCK 13 446 #define ECC_ENABLE_SELECT 14 447 #define WRITE_ENABLE_2_READ_ENABLE 15 448 #define ADDRESS_2_DATA 16 449 #define READ_ENABLE_2_WRITE_ENABLE 17 450 #define TWO_ROW_ADDRESS_CYCLES 18 451 #define MULTIPLANE_ADDRESS_RESTRICT 19 452 #define ACC_CLOCKS 20 453 #define READ_WRITE_ENABLE_LOW_COUNT 21 454 #define READ_WRITE_ENABLE_HIGH_COUNT 22 455 456 #define ECC_SECTOR_SIZE 512 457 458 #define DENALI_BUF_SIZE (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) 459 460 struct nand_buf { 461 int head; 462 int tail; 463 uint8_t buf[DENALI_BUF_SIZE]; 464 dma_addr_t dma_buf; 465 }; 466 467 #define INTEL_CE4100 1 468 #define INTEL_MRST 2 469 #define DT 3 470 471 struct denali_nand_info { 472 struct mtd_info mtd; 473 struct nand_chip nand; 474 int flash_bank; /* currently selected chip */ 475 int status; 476 int platform; 477 struct nand_buf buf; 478 struct device *dev; 479 int total_used_banks; 480 uint32_t block; /* stored for future use */ 481 uint16_t page; 482 void __iomem *flash_reg; /* Mapped io reg base address */ 483 void __iomem *flash_mem; /* Mapped io reg base address */ 484 485 /* elements used by ISR */ 486 struct completion complete; 487 spinlock_t irq_lock; 488 uint32_t irq_status; 489 int irq_debug_array[32]; 490 int idx; 491 int irq; 492 493 uint32_t devnum; /* represent how many nands connected */ 494 uint32_t fwblks; /* represent how many blocks FW used */ 495 uint32_t totalblks; 496 uint32_t blksperchip; 497 uint32_t bbtskipbytes; 498 uint32_t max_banks; 499 }; 500 501 extern int denali_init(struct denali_nand_info *denali); 502 extern void denali_remove(struct denali_nand_info *denali); 503 504 #endif /*_LLD_NAND_*/ 505