1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37 #ifndef MLX4_H
38 #define MLX4_H
39
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
46
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/driver.h>
49 #include <linux/mlx4/doorbell.h>
50 #include <linux/mlx4/cmd.h>
51
52 #define DRV_NAME "mlx4_core"
53 #define PFX DRV_NAME ": "
54 #define DRV_VERSION "1.1"
55 #define DRV_RELDATE "Dec, 2011"
56
57 #define MLX4_FS_UDP_UC_EN (1 << 1)
58 #define MLX4_FS_TCP_UC_EN (1 << 2)
59 #define MLX4_FS_NUM_OF_L2_ADDR 8
60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61 #define MLX4_FS_NUM_MCG (1 << 17)
62
63 #define INIT_HCA_TPT_MW_ENABLE (1 << 7)
64
65 #define MLX4_NUM_UP 8
66 #define MLX4_NUM_TC 8
67 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
68 #define MLX4_RATELIMIT_DEFAULT 0xffff
69
70 struct mlx4_set_port_prio2tc_context {
71 u8 prio2tc[4];
72 };
73
74 struct mlx4_port_scheduler_tc_cfg_be {
75 __be16 pg;
76 __be16 bw_precentage;
77 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
78 __be16 max_bw_value;
79 };
80
81 struct mlx4_set_port_scheduler_context {
82 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
83 };
84
85 enum {
86 MLX4_HCR_BASE = 0x80680,
87 MLX4_HCR_SIZE = 0x0001c,
88 MLX4_CLR_INT_SIZE = 0x00008,
89 MLX4_SLAVE_COMM_BASE = 0x0,
90 MLX4_COMM_PAGESIZE = 0x1000,
91 MLX4_CLOCK_SIZE = 0x00008
92 };
93
94 enum {
95 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
96 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
97 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
98 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
99 MLX4_MTT_ENTRY_PER_SEG = 8,
100 };
101
102 enum {
103 MLX4_NUM_PDS = 1 << 15
104 };
105
106 enum {
107 MLX4_CMPT_TYPE_QP = 0,
108 MLX4_CMPT_TYPE_SRQ = 1,
109 MLX4_CMPT_TYPE_CQ = 2,
110 MLX4_CMPT_TYPE_EQ = 3,
111 MLX4_CMPT_NUM_TYPE
112 };
113
114 enum {
115 MLX4_CMPT_SHIFT = 24,
116 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
117 };
118
119 enum mlx4_mpt_state {
120 MLX4_MPT_DISABLED = 0,
121 MLX4_MPT_EN_HW,
122 MLX4_MPT_EN_SW
123 };
124
125 #define MLX4_COMM_TIME 10000
126 enum {
127 MLX4_COMM_CMD_RESET,
128 MLX4_COMM_CMD_VHCR0,
129 MLX4_COMM_CMD_VHCR1,
130 MLX4_COMM_CMD_VHCR2,
131 MLX4_COMM_CMD_VHCR_EN,
132 MLX4_COMM_CMD_VHCR_POST,
133 MLX4_COMM_CMD_FLR = 254
134 };
135
136 /*The flag indicates that the slave should delay the RESET cmd*/
137 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
138 /*indicates how many retries will be done if we are in the middle of FLR*/
139 #define NUM_OF_RESET_RETRIES 10
140 #define SLEEP_TIME_IN_RESET (2 * 1000)
141 enum mlx4_resource {
142 RES_QP,
143 RES_CQ,
144 RES_SRQ,
145 RES_XRCD,
146 RES_MPT,
147 RES_MTT,
148 RES_MAC,
149 RES_VLAN,
150 RES_EQ,
151 RES_COUNTER,
152 RES_FS_RULE,
153 MLX4_NUM_OF_RESOURCE_TYPE
154 };
155
156 enum mlx4_alloc_mode {
157 RES_OP_RESERVE,
158 RES_OP_RESERVE_AND_MAP,
159 RES_OP_MAP_ICM,
160 };
161
162 enum mlx4_res_tracker_free_type {
163 RES_TR_FREE_ALL,
164 RES_TR_FREE_SLAVES_ONLY,
165 RES_TR_FREE_STRUCTS_ONLY,
166 };
167
168 /*
169 *Virtual HCR structures.
170 * mlx4_vhcr is the sw representation, in machine endianess
171 *
172 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
173 * to FW to go through communication channel.
174 * It is big endian, and has the same structure as the physical HCR
175 * used by command interface
176 */
177 struct mlx4_vhcr {
178 u64 in_param;
179 u64 out_param;
180 u32 in_modifier;
181 u32 errno;
182 u16 op;
183 u16 token;
184 u8 op_modifier;
185 u8 e_bit;
186 };
187
188 struct mlx4_vhcr_cmd {
189 __be64 in_param;
190 __be32 in_modifier;
191 __be64 out_param;
192 __be16 token;
193 u16 reserved;
194 u8 status;
195 u8 flags;
196 __be16 opcode;
197 };
198
199 struct mlx4_cmd_info {
200 u16 opcode;
201 bool has_inbox;
202 bool has_outbox;
203 bool out_is_imm;
204 bool encode_slave_id;
205 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
206 struct mlx4_cmd_mailbox *inbox);
207 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
208 struct mlx4_cmd_mailbox *inbox,
209 struct mlx4_cmd_mailbox *outbox,
210 struct mlx4_cmd_info *cmd);
211 };
212
213 #ifdef CONFIG_MLX4_DEBUG
214 extern int mlx4_debug_level;
215 #else /* CONFIG_MLX4_DEBUG */
216 #define mlx4_debug_level (0)
217 #endif /* CONFIG_MLX4_DEBUG */
218
219 #define mlx4_dbg(mdev, format, arg...) \
220 do { \
221 if (mlx4_debug_level) \
222 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
223 } while (0)
224
225 #define mlx4_err(mdev, format, arg...) \
226 dev_err(&mdev->pdev->dev, format, ##arg)
227 #define mlx4_info(mdev, format, arg...) \
228 dev_info(&mdev->pdev->dev, format, ##arg)
229 #define mlx4_warn(mdev, format, arg...) \
230 dev_warn(&mdev->pdev->dev, format, ##arg)
231
232 extern int mlx4_log_num_mgm_entry_size;
233 extern int log_mtts_per_seg;
234
235 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
236 #define ALL_SLAVES 0xff
237
238 struct mlx4_bitmap {
239 u32 last;
240 u32 top;
241 u32 max;
242 u32 reserved_top;
243 u32 mask;
244 u32 avail;
245 spinlock_t lock;
246 unsigned long *table;
247 };
248
249 struct mlx4_buddy {
250 unsigned long **bits;
251 unsigned int *num_free;
252 u32 max_order;
253 spinlock_t lock;
254 };
255
256 struct mlx4_icm;
257
258 struct mlx4_icm_table {
259 u64 virt;
260 int num_icm;
261 u32 num_obj;
262 int obj_size;
263 int lowmem;
264 int coherent;
265 struct mutex mutex;
266 struct mlx4_icm **icm;
267 };
268
269 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
270 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
271 #define MLX4_MPT_FLAG_MIO (1 << 17)
272 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
273 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
274 #define MLX4_MPT_FLAG_REGION (1 << 8)
275
276 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
277 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
278 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
279
280 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
281
282 #define MLX4_MPT_STATUS_SW 0xF0
283 #define MLX4_MPT_STATUS_HW 0x00
284
285 /*
286 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
287 */
288 struct mlx4_mpt_entry {
289 __be32 flags;
290 __be32 qpn;
291 __be32 key;
292 __be32 pd_flags;
293 __be64 start;
294 __be64 length;
295 __be32 lkey;
296 __be32 win_cnt;
297 u8 reserved1[3];
298 u8 mtt_rep;
299 __be64 mtt_addr;
300 __be32 mtt_sz;
301 __be32 entity_size;
302 __be32 first_byte_offset;
303 } __packed;
304
305 /*
306 * Must be packed because start is 64 bits but only aligned to 32 bits.
307 */
308 struct mlx4_eq_context {
309 __be32 flags;
310 u16 reserved1[3];
311 __be16 page_offset;
312 u8 log_eq_size;
313 u8 reserved2[4];
314 u8 eq_period;
315 u8 reserved3;
316 u8 eq_max_count;
317 u8 reserved4[3];
318 u8 intr;
319 u8 log_page_size;
320 u8 reserved5[2];
321 u8 mtt_base_addr_h;
322 __be32 mtt_base_addr_l;
323 u32 reserved6[2];
324 __be32 consumer_index;
325 __be32 producer_index;
326 u32 reserved7[4];
327 };
328
329 struct mlx4_cq_context {
330 __be32 flags;
331 u16 reserved1[3];
332 __be16 page_offset;
333 __be32 logsize_usrpage;
334 __be16 cq_period;
335 __be16 cq_max_count;
336 u8 reserved2[3];
337 u8 comp_eqn;
338 u8 log_page_size;
339 u8 reserved3[2];
340 u8 mtt_base_addr_h;
341 __be32 mtt_base_addr_l;
342 __be32 last_notified_index;
343 __be32 solicit_producer_index;
344 __be32 consumer_index;
345 __be32 producer_index;
346 u32 reserved4[2];
347 __be64 db_rec_addr;
348 };
349
350 struct mlx4_srq_context {
351 __be32 state_logsize_srqn;
352 u8 logstride;
353 u8 reserved1;
354 __be16 xrcd;
355 __be32 pg_offset_cqn;
356 u32 reserved2;
357 u8 log_page_size;
358 u8 reserved3[2];
359 u8 mtt_base_addr_h;
360 __be32 mtt_base_addr_l;
361 __be32 pd;
362 __be16 limit_watermark;
363 __be16 wqe_cnt;
364 u16 reserved4;
365 __be16 wqe_counter;
366 u32 reserved5;
367 __be64 db_rec_addr;
368 };
369
370 struct mlx4_eq {
371 struct mlx4_dev *dev;
372 void __iomem *doorbell;
373 int eqn;
374 u32 cons_index;
375 u16 irq;
376 u16 have_irq;
377 int nent;
378 struct mlx4_buf_list *page_list;
379 struct mlx4_mtt mtt;
380 };
381
382 struct mlx4_slave_eqe {
383 u8 type;
384 u8 port;
385 u32 param;
386 };
387
388 struct mlx4_slave_event_eq_info {
389 int eqn;
390 u16 token;
391 };
392
393 struct mlx4_profile {
394 int num_qp;
395 int rdmarc_per_qp;
396 int num_srq;
397 int num_cq;
398 int num_mcg;
399 int num_mpt;
400 unsigned num_mtt;
401 };
402
403 struct mlx4_fw {
404 u64 clr_int_base;
405 u64 catas_offset;
406 u64 comm_base;
407 u64 clock_offset;
408 struct mlx4_icm *fw_icm;
409 struct mlx4_icm *aux_icm;
410 u32 catas_size;
411 u16 fw_pages;
412 u8 clr_int_bar;
413 u8 catas_bar;
414 u8 comm_bar;
415 u8 clock_bar;
416 };
417
418 struct mlx4_comm {
419 u32 slave_write;
420 u32 slave_read;
421 };
422
423 enum {
424 MLX4_MCAST_CONFIG = 0,
425 MLX4_MCAST_DISABLE = 1,
426 MLX4_MCAST_ENABLE = 2,
427 };
428
429 #define VLAN_FLTR_SIZE 128
430
431 struct mlx4_vlan_fltr {
432 __be32 entry[VLAN_FLTR_SIZE];
433 };
434
435 struct mlx4_mcast_entry {
436 struct list_head list;
437 u64 addr;
438 };
439
440 struct mlx4_promisc_qp {
441 struct list_head list;
442 u32 qpn;
443 };
444
445 struct mlx4_steer_index {
446 struct list_head list;
447 unsigned int index;
448 struct list_head duplicates;
449 };
450
451 #define MLX4_EVENT_TYPES_NUM 64
452
453 struct mlx4_slave_state {
454 u8 comm_toggle;
455 u8 last_cmd;
456 u8 init_port_mask;
457 bool active;
458 u8 function;
459 dma_addr_t vhcr_dma;
460 u16 mtu[MLX4_MAX_PORTS + 1];
461 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
462 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
463 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
464 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
465 /* event type to eq number lookup */
466 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
467 u16 eq_pi;
468 u16 eq_ci;
469 spinlock_t lock;
470 /*initialized via the kzalloc*/
471 u8 is_slave_going_down;
472 u32 cookie;
473 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
474 };
475
476 #define MLX4_VGT 4095
477 #define NO_INDX (-1)
478
479 struct mlx4_vport_state {
480 u64 mac;
481 u16 default_vlan;
482 u8 default_qos;
483 u32 tx_rate;
484 bool spoofchk;
485 };
486
487 struct mlx4_vf_admin_state {
488 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
489 };
490
491 struct mlx4_vport_oper_state {
492 struct mlx4_vport_state state;
493 int mac_idx;
494 int vlan_idx;
495 };
496 struct mlx4_vf_oper_state {
497 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
498 };
499
500 struct slave_list {
501 struct mutex mutex;
502 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
503 };
504
505 struct mlx4_resource_tracker {
506 spinlock_t lock;
507 /* tree for each resources */
508 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
509 /* num_of_slave's lists, one per slave */
510 struct slave_list *slave_list;
511 };
512
513 #define SLAVE_EVENT_EQ_SIZE 128
514 struct mlx4_slave_event_eq {
515 u32 eqn;
516 u32 cons;
517 u32 prod;
518 spinlock_t event_lock;
519 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
520 };
521
522 struct mlx4_master_qp0_state {
523 int proxy_qp0_active;
524 int qp0_active;
525 int port_active;
526 };
527
528 struct mlx4_mfunc_master_ctx {
529 struct mlx4_slave_state *slave_state;
530 struct mlx4_vf_admin_state *vf_admin;
531 struct mlx4_vf_oper_state *vf_oper;
532 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
533 int init_port_ref[MLX4_MAX_PORTS + 1];
534 u16 max_mtu[MLX4_MAX_PORTS + 1];
535 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
536 struct mlx4_resource_tracker res_tracker;
537 struct workqueue_struct *comm_wq;
538 struct work_struct comm_work;
539 struct work_struct slave_event_work;
540 struct work_struct slave_flr_event_work;
541 spinlock_t slave_state_lock;
542 __be32 comm_arm_bit_vector[4];
543 struct mlx4_eqe cmd_eqe;
544 struct mlx4_slave_event_eq slave_eq;
545 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
546 };
547
548 struct mlx4_mfunc {
549 struct mlx4_comm __iomem *comm;
550 struct mlx4_vhcr_cmd *vhcr;
551 dma_addr_t vhcr_dma;
552
553 struct mlx4_mfunc_master_ctx master;
554 };
555
556 struct mlx4_cmd {
557 struct pci_pool *pool;
558 void __iomem *hcr;
559 struct mutex hcr_mutex;
560 struct mutex slave_cmd_mutex;
561 struct semaphore poll_sem;
562 struct semaphore event_sem;
563 int max_cmds;
564 spinlock_t context_lock;
565 int free_head;
566 struct mlx4_cmd_context *context;
567 u16 token_mask;
568 u8 use_events;
569 u8 toggle;
570 u8 comm_toggle;
571 };
572
573 struct mlx4_uar_table {
574 struct mlx4_bitmap bitmap;
575 };
576
577 struct mlx4_mr_table {
578 struct mlx4_bitmap mpt_bitmap;
579 struct mlx4_buddy mtt_buddy;
580 u64 mtt_base;
581 u64 mpt_base;
582 struct mlx4_icm_table mtt_table;
583 struct mlx4_icm_table dmpt_table;
584 };
585
586 struct mlx4_cq_table {
587 struct mlx4_bitmap bitmap;
588 spinlock_t lock;
589 struct radix_tree_root tree;
590 struct mlx4_icm_table table;
591 struct mlx4_icm_table cmpt_table;
592 };
593
594 struct mlx4_eq_table {
595 struct mlx4_bitmap bitmap;
596 char *irq_names;
597 void __iomem *clr_int;
598 void __iomem **uar_map;
599 u32 clr_mask;
600 struct mlx4_eq *eq;
601 struct mlx4_icm_table table;
602 struct mlx4_icm_table cmpt_table;
603 int have_irq;
604 u8 inta_pin;
605 };
606
607 struct mlx4_srq_table {
608 struct mlx4_bitmap bitmap;
609 spinlock_t lock;
610 struct radix_tree_root tree;
611 struct mlx4_icm_table table;
612 struct mlx4_icm_table cmpt_table;
613 };
614
615 struct mlx4_qp_table {
616 struct mlx4_bitmap bitmap;
617 u32 rdmarc_base;
618 int rdmarc_shift;
619 spinlock_t lock;
620 struct mlx4_icm_table qp_table;
621 struct mlx4_icm_table auxc_table;
622 struct mlx4_icm_table altc_table;
623 struct mlx4_icm_table rdmarc_table;
624 struct mlx4_icm_table cmpt_table;
625 };
626
627 struct mlx4_mcg_table {
628 struct mutex mutex;
629 struct mlx4_bitmap bitmap;
630 struct mlx4_icm_table table;
631 };
632
633 struct mlx4_catas_err {
634 u32 __iomem *map;
635 struct timer_list timer;
636 struct list_head list;
637 };
638
639 #define MLX4_MAX_MAC_NUM 128
640 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
641
642 struct mlx4_mac_table {
643 __be64 entries[MLX4_MAX_MAC_NUM];
644 int refs[MLX4_MAX_MAC_NUM];
645 struct mutex mutex;
646 int total;
647 int max;
648 };
649
650 #define MLX4_MAX_VLAN_NUM 128
651 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
652
653 struct mlx4_vlan_table {
654 __be32 entries[MLX4_MAX_VLAN_NUM];
655 int refs[MLX4_MAX_VLAN_NUM];
656 struct mutex mutex;
657 int total;
658 int max;
659 };
660
661 #define SET_PORT_GEN_ALL_VALID 0x7
662 #define SET_PORT_PROMISC_SHIFT 31
663 #define SET_PORT_MC_PROMISC_SHIFT 30
664
665 enum {
666 MCAST_DIRECT_ONLY = 0,
667 MCAST_DIRECT = 1,
668 MCAST_DEFAULT = 2
669 };
670
671
672 struct mlx4_set_port_general_context {
673 u8 reserved[3];
674 u8 flags;
675 u16 reserved2;
676 __be16 mtu;
677 u8 pptx;
678 u8 pfctx;
679 u16 reserved3;
680 u8 pprx;
681 u8 pfcrx;
682 u16 reserved4;
683 };
684
685 struct mlx4_set_port_rqp_calc_context {
686 __be32 base_qpn;
687 u8 rererved;
688 u8 n_mac;
689 u8 n_vlan;
690 u8 n_prio;
691 u8 reserved2[3];
692 u8 mac_miss;
693 u8 intra_no_vlan;
694 u8 no_vlan;
695 u8 intra_vlan_miss;
696 u8 vlan_miss;
697 u8 reserved3[3];
698 u8 no_vlan_prio;
699 __be32 promisc;
700 __be32 mcast;
701 };
702
703 struct mlx4_port_info {
704 struct mlx4_dev *dev;
705 int port;
706 char dev_name[16];
707 struct device_attribute port_attr;
708 enum mlx4_port_type tmp_type;
709 char dev_mtu_name[16];
710 struct device_attribute port_mtu_attr;
711 struct mlx4_mac_table mac_table;
712 struct mlx4_vlan_table vlan_table;
713 int base_qpn;
714 };
715
716 struct mlx4_sense {
717 struct mlx4_dev *dev;
718 u8 do_sense_port[MLX4_MAX_PORTS + 1];
719 u8 sense_allowed[MLX4_MAX_PORTS + 1];
720 struct delayed_work sense_poll;
721 };
722
723 struct mlx4_msix_ctl {
724 u64 pool_bm;
725 struct mutex pool_lock;
726 };
727
728 struct mlx4_steer {
729 struct list_head promisc_qps[MLX4_NUM_STEERS];
730 struct list_head steer_entries[MLX4_NUM_STEERS];
731 };
732
733 enum {
734 MLX4_PCI_DEV_IS_VF = 1 << 0,
735 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
736 };
737
738 struct mlx4_priv {
739 struct mlx4_dev dev;
740
741 struct list_head dev_list;
742 struct list_head ctx_list;
743 spinlock_t ctx_lock;
744
745 int pci_dev_data;
746
747 struct list_head pgdir_list;
748 struct mutex pgdir_mutex;
749
750 struct mlx4_fw fw;
751 struct mlx4_cmd cmd;
752 struct mlx4_mfunc mfunc;
753
754 struct mlx4_bitmap pd_bitmap;
755 struct mlx4_bitmap xrcd_bitmap;
756 struct mlx4_uar_table uar_table;
757 struct mlx4_mr_table mr_table;
758 struct mlx4_cq_table cq_table;
759 struct mlx4_eq_table eq_table;
760 struct mlx4_srq_table srq_table;
761 struct mlx4_qp_table qp_table;
762 struct mlx4_mcg_table mcg_table;
763 struct mlx4_bitmap counters_bitmap;
764
765 struct mlx4_catas_err catas_err;
766
767 void __iomem *clr_base;
768
769 struct mlx4_uar driver_uar;
770 void __iomem *kar;
771 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
772 struct mlx4_sense sense;
773 struct mutex port_mutex;
774 struct mlx4_msix_ctl msix_ctl;
775 struct mlx4_steer *steer;
776 struct list_head bf_list;
777 struct mutex bf_mutex;
778 struct io_mapping *bf_mapping;
779 void __iomem *clock_mapping;
780 int reserved_mtts;
781 int fs_hash_mode;
782 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
783 __be64 slave_node_guids[MLX4_MFUNC_MAX];
784
785 };
786
mlx4_priv(struct mlx4_dev * dev)787 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
788 {
789 return container_of(dev, struct mlx4_priv, dev);
790 }
791
792 #define MLX4_SENSE_RANGE (HZ * 3)
793
794 extern struct workqueue_struct *mlx4_wq;
795
796 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
797 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
798 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
799 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
800 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
801 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
802 u32 reserved_bot, u32 resetrved_top);
803 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
804
805 int mlx4_reset(struct mlx4_dev *dev);
806
807 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
808 void mlx4_free_eq_table(struct mlx4_dev *dev);
809
810 int mlx4_init_pd_table(struct mlx4_dev *dev);
811 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
812 int mlx4_init_uar_table(struct mlx4_dev *dev);
813 int mlx4_init_mr_table(struct mlx4_dev *dev);
814 int mlx4_init_eq_table(struct mlx4_dev *dev);
815 int mlx4_init_cq_table(struct mlx4_dev *dev);
816 int mlx4_init_qp_table(struct mlx4_dev *dev);
817 int mlx4_init_srq_table(struct mlx4_dev *dev);
818 int mlx4_init_mcg_table(struct mlx4_dev *dev);
819
820 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
821 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
822 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
823 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
824 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
825 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
826 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
827 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
828 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
829 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
830 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
831 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
832 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
833 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
834 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
835 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
836 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
837 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index);
838 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
839 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
840 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
841
842 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
843 struct mlx4_vhcr *vhcr,
844 struct mlx4_cmd_mailbox *inbox,
845 struct mlx4_cmd_mailbox *outbox,
846 struct mlx4_cmd_info *cmd);
847 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
848 struct mlx4_vhcr *vhcr,
849 struct mlx4_cmd_mailbox *inbox,
850 struct mlx4_cmd_mailbox *outbox,
851 struct mlx4_cmd_info *cmd);
852 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
853 struct mlx4_vhcr *vhcr,
854 struct mlx4_cmd_mailbox *inbox,
855 struct mlx4_cmd_mailbox *outbox,
856 struct mlx4_cmd_info *cmd);
857 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
858 struct mlx4_vhcr *vhcr,
859 struct mlx4_cmd_mailbox *inbox,
860 struct mlx4_cmd_mailbox *outbox,
861 struct mlx4_cmd_info *cmd);
862 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
863 struct mlx4_vhcr *vhcr,
864 struct mlx4_cmd_mailbox *inbox,
865 struct mlx4_cmd_mailbox *outbox,
866 struct mlx4_cmd_info *cmd);
867 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
868 struct mlx4_vhcr *vhcr,
869 struct mlx4_cmd_mailbox *inbox,
870 struct mlx4_cmd_mailbox *outbox,
871 struct mlx4_cmd_info *cmd);
872 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
873 struct mlx4_vhcr *vhcr,
874 struct mlx4_cmd_mailbox *inbox,
875 struct mlx4_cmd_mailbox *outbox,
876 struct mlx4_cmd_info *cmd);
877 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
878 int *base);
879 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
880 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
881 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
882 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
883 int start_index, int npages, u64 *page_list);
884 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
885 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
886 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
887 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
888
889 void mlx4_start_catas_poll(struct mlx4_dev *dev);
890 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
891 void mlx4_catas_init(void);
892 int mlx4_restart_one(struct pci_dev *pdev);
893 int mlx4_register_device(struct mlx4_dev *dev);
894 void mlx4_unregister_device(struct mlx4_dev *dev);
895 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
896 unsigned long param);
897
898 struct mlx4_dev_cap;
899 struct mlx4_init_hca_param;
900
901 u64 mlx4_make_profile(struct mlx4_dev *dev,
902 struct mlx4_profile *request,
903 struct mlx4_dev_cap *dev_cap,
904 struct mlx4_init_hca_param *init_hca);
905 void mlx4_master_comm_channel(struct work_struct *work);
906 void mlx4_gen_slave_eqe(struct work_struct *work);
907 void mlx4_master_handle_slave_flr(struct work_struct *work);
908
909 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
910 struct mlx4_vhcr *vhcr,
911 struct mlx4_cmd_mailbox *inbox,
912 struct mlx4_cmd_mailbox *outbox,
913 struct mlx4_cmd_info *cmd);
914 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
915 struct mlx4_vhcr *vhcr,
916 struct mlx4_cmd_mailbox *inbox,
917 struct mlx4_cmd_mailbox *outbox,
918 struct mlx4_cmd_info *cmd);
919 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
920 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
921 struct mlx4_cmd_mailbox *outbox,
922 struct mlx4_cmd_info *cmd);
923 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
924 struct mlx4_vhcr *vhcr,
925 struct mlx4_cmd_mailbox *inbox,
926 struct mlx4_cmd_mailbox *outbox,
927 struct mlx4_cmd_info *cmd);
928 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
929 struct mlx4_vhcr *vhcr,
930 struct mlx4_cmd_mailbox *inbox,
931 struct mlx4_cmd_mailbox *outbox,
932 struct mlx4_cmd_info *cmd);
933 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
934 struct mlx4_vhcr *vhcr,
935 struct mlx4_cmd_mailbox *inbox,
936 struct mlx4_cmd_mailbox *outbox,
937 struct mlx4_cmd_info *cmd);
938 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
939 struct mlx4_vhcr *vhcr,
940 struct mlx4_cmd_mailbox *inbox,
941 struct mlx4_cmd_mailbox *outbox,
942 struct mlx4_cmd_info *cmd);
943 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
944 struct mlx4_vhcr *vhcr,
945 struct mlx4_cmd_mailbox *inbox,
946 struct mlx4_cmd_mailbox *outbox,
947 struct mlx4_cmd_info *cmd);
948 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
949 struct mlx4_vhcr *vhcr,
950 struct mlx4_cmd_mailbox *inbox,
951 struct mlx4_cmd_mailbox *outbox,
952 struct mlx4_cmd_info *cmd);
953 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
954 struct mlx4_vhcr *vhcr,
955 struct mlx4_cmd_mailbox *inbox,
956 struct mlx4_cmd_mailbox *outbox,
957 struct mlx4_cmd_info *cmd);
958 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
959 struct mlx4_vhcr *vhcr,
960 struct mlx4_cmd_mailbox *inbox,
961 struct mlx4_cmd_mailbox *outbox,
962 struct mlx4_cmd_info *cmd);
963 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
964 struct mlx4_vhcr *vhcr,
965 struct mlx4_cmd_mailbox *inbox,
966 struct mlx4_cmd_mailbox *outbox,
967 struct mlx4_cmd_info *cmd);
968 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
969 struct mlx4_vhcr *vhcr,
970 struct mlx4_cmd_mailbox *inbox,
971 struct mlx4_cmd_mailbox *outbox,
972 struct mlx4_cmd_info *cmd);
973 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
974 struct mlx4_vhcr *vhcr,
975 struct mlx4_cmd_mailbox *inbox,
976 struct mlx4_cmd_mailbox *outbox,
977 struct mlx4_cmd_info *cmd);
978 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
979 struct mlx4_vhcr *vhcr,
980 struct mlx4_cmd_mailbox *inbox,
981 struct mlx4_cmd_mailbox *outbox,
982 struct mlx4_cmd_info *cmd);
983 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
984 struct mlx4_vhcr *vhcr,
985 struct mlx4_cmd_mailbox *inbox,
986 struct mlx4_cmd_mailbox *outbox,
987 struct mlx4_cmd_info *cmd);
988 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
989 struct mlx4_vhcr *vhcr,
990 struct mlx4_cmd_mailbox *inbox,
991 struct mlx4_cmd_mailbox *outbox,
992 struct mlx4_cmd_info *cmd);
993 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
994 struct mlx4_vhcr *vhcr,
995 struct mlx4_cmd_mailbox *inbox,
996 struct mlx4_cmd_mailbox *outbox,
997 struct mlx4_cmd_info *cmd);
998 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
999 struct mlx4_vhcr *vhcr,
1000 struct mlx4_cmd_mailbox *inbox,
1001 struct mlx4_cmd_mailbox *outbox,
1002 struct mlx4_cmd_info *cmd);
1003 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1004 struct mlx4_vhcr *vhcr,
1005 struct mlx4_cmd_mailbox *inbox,
1006 struct mlx4_cmd_mailbox *outbox,
1007 struct mlx4_cmd_info *cmd);
1008 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1009 struct mlx4_vhcr *vhcr,
1010 struct mlx4_cmd_mailbox *inbox,
1011 struct mlx4_cmd_mailbox *outbox,
1012 struct mlx4_cmd_info *cmd);
1013 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1014 struct mlx4_vhcr *vhcr,
1015 struct mlx4_cmd_mailbox *inbox,
1016 struct mlx4_cmd_mailbox *outbox,
1017 struct mlx4_cmd_info *cmd);
1018 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1019 struct mlx4_vhcr *vhcr,
1020 struct mlx4_cmd_mailbox *inbox,
1021 struct mlx4_cmd_mailbox *outbox,
1022 struct mlx4_cmd_info *cmd);
1023 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1024 struct mlx4_vhcr *vhcr,
1025 struct mlx4_cmd_mailbox *inbox,
1026 struct mlx4_cmd_mailbox *outbox,
1027 struct mlx4_cmd_info *cmd);
1028 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1029 struct mlx4_vhcr *vhcr,
1030 struct mlx4_cmd_mailbox *inbox,
1031 struct mlx4_cmd_mailbox *outbox,
1032 struct mlx4_cmd_info *cmd);
1033 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1034 struct mlx4_vhcr *vhcr,
1035 struct mlx4_cmd_mailbox *inbox,
1036 struct mlx4_cmd_mailbox *outbox,
1037 struct mlx4_cmd_info *cmd);
1038 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1039 struct mlx4_vhcr *vhcr,
1040 struct mlx4_cmd_mailbox *inbox,
1041 struct mlx4_cmd_mailbox *outbox,
1042 struct mlx4_cmd_info *cmd);
1043
1044 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1045
1046 int mlx4_cmd_init(struct mlx4_dev *dev);
1047 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1048 int mlx4_multi_func_init(struct mlx4_dev *dev);
1049 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1050 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1051 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1052 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1053
1054 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1055 unsigned long timeout);
1056
1057 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1058 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1059
1060 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1061
1062 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1063
1064 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1065
1066 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1067 enum mlx4_port_type *type);
1068 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1069 enum mlx4_port_type *stype,
1070 enum mlx4_port_type *defaults);
1071 void mlx4_start_sense(struct mlx4_dev *dev);
1072 void mlx4_stop_sense(struct mlx4_dev *dev);
1073 void mlx4_sense_init(struct mlx4_dev *dev);
1074 int mlx4_check_port_params(struct mlx4_dev *dev,
1075 enum mlx4_port_type *port_type);
1076 int mlx4_change_port_types(struct mlx4_dev *dev,
1077 enum mlx4_port_type *port_types);
1078
1079 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1080 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1081 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
1082 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1083
1084 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1085 /* resource tracker functions*/
1086 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1087 enum mlx4_resource resource_type,
1088 u64 resource_id, int *slave);
1089 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1090 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1091
1092 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1093 enum mlx4_res_tracker_free_type type);
1094
1095 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1096 struct mlx4_vhcr *vhcr,
1097 struct mlx4_cmd_mailbox *inbox,
1098 struct mlx4_cmd_mailbox *outbox,
1099 struct mlx4_cmd_info *cmd);
1100 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1101 struct mlx4_vhcr *vhcr,
1102 struct mlx4_cmd_mailbox *inbox,
1103 struct mlx4_cmd_mailbox *outbox,
1104 struct mlx4_cmd_info *cmd);
1105 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1106 struct mlx4_vhcr *vhcr,
1107 struct mlx4_cmd_mailbox *inbox,
1108 struct mlx4_cmd_mailbox *outbox,
1109 struct mlx4_cmd_info *cmd);
1110 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1111 struct mlx4_vhcr *vhcr,
1112 struct mlx4_cmd_mailbox *inbox,
1113 struct mlx4_cmd_mailbox *outbox,
1114 struct mlx4_cmd_info *cmd);
1115 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1116 struct mlx4_vhcr *vhcr,
1117 struct mlx4_cmd_mailbox *inbox,
1118 struct mlx4_cmd_mailbox *outbox,
1119 struct mlx4_cmd_info *cmd);
1120 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1121 struct mlx4_vhcr *vhcr,
1122 struct mlx4_cmd_mailbox *inbox,
1123 struct mlx4_cmd_mailbox *outbox,
1124 struct mlx4_cmd_info *cmd);
1125 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1126
1127 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1128 int *gid_tbl_len, int *pkey_tbl_len);
1129
1130 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1131 struct mlx4_vhcr *vhcr,
1132 struct mlx4_cmd_mailbox *inbox,
1133 struct mlx4_cmd_mailbox *outbox,
1134 struct mlx4_cmd_info *cmd);
1135
1136 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1137 struct mlx4_vhcr *vhcr,
1138 struct mlx4_cmd_mailbox *inbox,
1139 struct mlx4_cmd_mailbox *outbox,
1140 struct mlx4_cmd_info *cmd);
1141 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1142 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1143 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1144 int block_mcast_loopback, enum mlx4_protocol prot,
1145 enum mlx4_steer_type steer);
1146 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1147 u8 gid[16], u8 port,
1148 int block_mcast_loopback,
1149 enum mlx4_protocol prot, u64 *reg_id);
1150 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1151 struct mlx4_vhcr *vhcr,
1152 struct mlx4_cmd_mailbox *inbox,
1153 struct mlx4_cmd_mailbox *outbox,
1154 struct mlx4_cmd_info *cmd);
1155 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1156 struct mlx4_vhcr *vhcr,
1157 struct mlx4_cmd_mailbox *inbox,
1158 struct mlx4_cmd_mailbox *outbox,
1159 struct mlx4_cmd_info *cmd);
1160 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1161 int port, void *buf);
1162 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1163 struct mlx4_cmd_mailbox *outbox);
1164 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1165 struct mlx4_vhcr *vhcr,
1166 struct mlx4_cmd_mailbox *inbox,
1167 struct mlx4_cmd_mailbox *outbox,
1168 struct mlx4_cmd_info *cmd);
1169 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1170 struct mlx4_vhcr *vhcr,
1171 struct mlx4_cmd_mailbox *inbox,
1172 struct mlx4_cmd_mailbox *outbox,
1173 struct mlx4_cmd_info *cmd);
1174 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1175 struct mlx4_vhcr *vhcr,
1176 struct mlx4_cmd_mailbox *inbox,
1177 struct mlx4_cmd_mailbox *outbox,
1178 struct mlx4_cmd_info *cmd);
1179 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1180 struct mlx4_vhcr *vhcr,
1181 struct mlx4_cmd_mailbox *inbox,
1182 struct mlx4_cmd_mailbox *outbox,
1183 struct mlx4_cmd_info *cmd);
1184 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1185 struct mlx4_vhcr *vhcr,
1186 struct mlx4_cmd_mailbox *inbox,
1187 struct mlx4_cmd_mailbox *outbox,
1188 struct mlx4_cmd_info *cmd);
1189
1190 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1191 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1192
set_param_l(u64 * arg,u32 val)1193 static inline void set_param_l(u64 *arg, u32 val)
1194 {
1195 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1196 }
1197
set_param_h(u64 * arg,u32 val)1198 static inline void set_param_h(u64 *arg, u32 val)
1199 {
1200 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1201 }
1202
get_param_l(u64 * arg)1203 static inline u32 get_param_l(u64 *arg)
1204 {
1205 return (u32) (*arg & 0xffffffff);
1206 }
1207
get_param_h(u64 * arg)1208 static inline u32 get_param_h(u64 *arg)
1209 {
1210 return (u32)(*arg >> 32);
1211 }
1212
mlx4_tlock(struct mlx4_dev * dev)1213 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1214 {
1215 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1216 }
1217
1218 #define NOT_MASKED_PD_BITS 17
1219
1220 #endif /* MLX4_H */
1221