1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2011 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 /* Common definitions for all Efx net driver code */
12
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
15
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/if_vlan.h>
20 #include <linux/timer.h>
21 #include <linux/mdio.h>
22 #include <linux/list.h>
23 #include <linux/pci.h>
24 #include <linux/device.h>
25 #include <linux/highmem.h>
26 #include <linux/workqueue.h>
27 #include <linux/mutex.h>
28 #include <linux/vmalloc.h>
29 #include <linux/i2c.h>
30
31 #include "enum.h"
32 #include "bitfield.h"
33
34 /**************************************************************************
35 *
36 * Build definitions
37 *
38 **************************************************************************/
39
40 #define EFX_DRIVER_VERSION "3.2"
41
42 #ifdef DEBUG
43 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
44 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
45 #else
46 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
47 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
48 #endif
49
50 /**************************************************************************
51 *
52 * Efx data structures
53 *
54 **************************************************************************/
55
56 #define EFX_MAX_CHANNELS 32U
57 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
58 #define EFX_EXTRA_CHANNEL_IOV 0
59 #define EFX_EXTRA_CHANNEL_PTP 1
60 #define EFX_MAX_EXTRA_CHANNELS 2U
61
62 /* Checksum generation is a per-queue option in hardware, so each
63 * queue visible to the networking core is backed by two hardware TX
64 * queues. */
65 #define EFX_MAX_TX_TC 2
66 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
67 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */
68 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */
69 #define EFX_TXQ_TYPES 4
70 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS)
71
72 /* Maximum possible MTU the driver supports */
73 #define EFX_MAX_MTU (9 * 1024)
74
75 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page,
76 * and should be a multiple of the cache line size.
77 */
78 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
79
80 /* If possible, we should ensure cache line alignment at start and end
81 * of every buffer. Otherwise, we just need to ensure 4-byte
82 * alignment of the network header.
83 */
84 #if NET_IP_ALIGN == 0
85 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES
86 #else
87 #define EFX_RX_BUF_ALIGNMENT 4
88 #endif
89
90 /* Forward declare Precision Time Protocol (PTP) support structure. */
91 struct efx_ptp_data;
92
93 struct efx_self_tests;
94
95 /**
96 * struct efx_special_buffer - An Efx special buffer
97 * @addr: CPU base address of the buffer
98 * @dma_addr: DMA base address of the buffer
99 * @len: Buffer length, in bytes
100 * @index: Buffer index within controller;s buffer table
101 * @entries: Number of buffer table entries
102 *
103 * Special buffers are used for the event queues and the TX and RX
104 * descriptor queues for each channel. They are *not* used for the
105 * actual transmit and receive buffers.
106 */
107 struct efx_special_buffer {
108 void *addr;
109 dma_addr_t dma_addr;
110 unsigned int len;
111 unsigned int index;
112 unsigned int entries;
113 };
114
115 /**
116 * struct efx_tx_buffer - buffer state for a TX descriptor
117 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be
118 * freed when descriptor completes
119 * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be
120 * freed when descriptor completes.
121 * @dma_addr: DMA address of the fragment.
122 * @flags: Flags for allocation and DMA mapping type
123 * @len: Length of this fragment.
124 * This field is zero when the queue slot is empty.
125 * @unmap_len: Length of this fragment to unmap
126 */
127 struct efx_tx_buffer {
128 union {
129 const struct sk_buff *skb;
130 void *heap_buf;
131 };
132 dma_addr_t dma_addr;
133 unsigned short flags;
134 unsigned short len;
135 unsigned short unmap_len;
136 };
137 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */
138 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */
139 #define EFX_TX_BUF_HEAP 4 /* buffer was allocated with kmalloc() */
140 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */
141
142 /**
143 * struct efx_tx_queue - An Efx TX queue
144 *
145 * This is a ring buffer of TX fragments.
146 * Since the TX completion path always executes on the same
147 * CPU and the xmit path can operate on different CPUs,
148 * performance is increased by ensuring that the completion
149 * path and the xmit path operate on different cache lines.
150 * This is particularly important if the xmit path is always
151 * executing on one CPU which is different from the completion
152 * path. There is also a cache line for members which are
153 * read but not written on the fast path.
154 *
155 * @efx: The associated Efx NIC
156 * @queue: DMA queue number
157 * @channel: The associated channel
158 * @core_txq: The networking core TX queue structure
159 * @buffer: The software buffer ring
160 * @tsoh_page: Array of pages of TSO header buffers
161 * @txd: The hardware descriptor ring
162 * @ptr_mask: The size of the ring minus 1.
163 * @initialised: Has hardware queue been initialised?
164 * @read_count: Current read pointer.
165 * This is the number of buffers that have been removed from both rings.
166 * @old_write_count: The value of @write_count when last checked.
167 * This is here for performance reasons. The xmit path will
168 * only get the up-to-date value of @write_count if this
169 * variable indicates that the queue is empty. This is to
170 * avoid cache-line ping-pong between the xmit path and the
171 * completion path.
172 * @insert_count: Current insert pointer
173 * This is the number of buffers that have been added to the
174 * software ring.
175 * @write_count: Current write pointer
176 * This is the number of buffers that have been added to the
177 * hardware ring.
178 * @old_read_count: The value of read_count when last checked.
179 * This is here for performance reasons. The xmit path will
180 * only get the up-to-date value of read_count if this
181 * variable indicates that the queue is full. This is to
182 * avoid cache-line ping-pong between the xmit path and the
183 * completion path.
184 * @tso_bursts: Number of times TSO xmit invoked by kernel
185 * @tso_long_headers: Number of packets with headers too long for standard
186 * blocks
187 * @tso_packets: Number of packets via the TSO xmit path
188 * @pushes: Number of times the TX push feature has been used
189 * @empty_read_count: If the completion path has seen the queue as empty
190 * and the transmission path has not yet checked this, the value of
191 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
192 */
193 struct efx_tx_queue {
194 /* Members which don't change on the fast path */
195 struct efx_nic *efx ____cacheline_aligned_in_smp;
196 unsigned queue;
197 struct efx_channel *channel;
198 struct netdev_queue *core_txq;
199 struct efx_tx_buffer *buffer;
200 struct efx_buffer *tsoh_page;
201 struct efx_special_buffer txd;
202 unsigned int ptr_mask;
203 bool initialised;
204
205 /* Members used mainly on the completion path */
206 unsigned int read_count ____cacheline_aligned_in_smp;
207 unsigned int old_write_count;
208
209 /* Members used only on the xmit path */
210 unsigned int insert_count ____cacheline_aligned_in_smp;
211 unsigned int write_count;
212 unsigned int old_read_count;
213 unsigned int tso_bursts;
214 unsigned int tso_long_headers;
215 unsigned int tso_packets;
216 unsigned int pushes;
217
218 /* Members shared between paths and sometimes updated */
219 unsigned int empty_read_count ____cacheline_aligned_in_smp;
220 #define EFX_EMPTY_COUNT_VALID 0x80000000
221 atomic_t flush_outstanding;
222 };
223
224 /**
225 * struct efx_rx_buffer - An Efx RX data buffer
226 * @dma_addr: DMA base address of the buffer
227 * @page: The associated page buffer.
228 * Will be %NULL if the buffer slot is currently free.
229 * @page_offset: If pending: offset in @page of DMA base address.
230 * If completed: offset in @page of Ethernet header.
231 * @len: If pending: length for DMA descriptor.
232 * If completed: received length, excluding hash prefix.
233 * @flags: Flags for buffer and packet state. These are only set on the
234 * first buffer of a scattered packet.
235 */
236 struct efx_rx_buffer {
237 dma_addr_t dma_addr;
238 struct page *page;
239 u16 page_offset;
240 u16 len;
241 u16 flags;
242 };
243 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001
244 #define EFX_RX_PKT_CSUMMED 0x0002
245 #define EFX_RX_PKT_DISCARD 0x0004
246
247 /**
248 * struct efx_rx_page_state - Page-based rx buffer state
249 *
250 * Inserted at the start of every page allocated for receive buffers.
251 * Used to facilitate sharing dma mappings between recycled rx buffers
252 * and those passed up to the kernel.
253 *
254 * @refcnt: Number of struct efx_rx_buffer's referencing this page.
255 * When refcnt falls to zero, the page is unmapped for dma
256 * @dma_addr: The dma address of this page.
257 */
258 struct efx_rx_page_state {
259 unsigned refcnt;
260 dma_addr_t dma_addr;
261
262 unsigned int __pad[0] ____cacheline_aligned;
263 };
264
265 /**
266 * struct efx_rx_queue - An Efx RX queue
267 * @efx: The associated Efx NIC
268 * @core_index: Index of network core RX queue. Will be >= 0 iff this
269 * is associated with a real RX queue.
270 * @buffer: The software buffer ring
271 * @rxd: The hardware descriptor ring
272 * @ptr_mask: The size of the ring minus 1.
273 * @enabled: Receive queue enabled indicator.
274 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
275 * @rxq_flush_pending.
276 * @added_count: Number of buffers added to the receive queue.
277 * @notified_count: Number of buffers given to NIC (<= @added_count).
278 * @removed_count: Number of buffers removed from the receive queue.
279 * @scatter_n: Number of buffers used by current packet
280 * @page_ring: The ring to store DMA mapped pages for reuse.
281 * @page_add: Counter to calculate the write pointer for the recycle ring.
282 * @page_remove: Counter to calculate the read pointer for the recycle ring.
283 * @page_recycle_count: The number of pages that have been recycled.
284 * @page_recycle_failed: The number of pages that couldn't be recycled because
285 * the kernel still held a reference to them.
286 * @page_recycle_full: The number of pages that were released because the
287 * recycle ring was full.
288 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
289 * @max_fill: RX descriptor maximum fill level (<= ring size)
290 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
291 * (<= @max_fill)
292 * @min_fill: RX descriptor minimum non-zero fill level.
293 * This records the minimum fill level observed when a ring
294 * refill was triggered.
295 * @recycle_count: RX buffer recycle counter.
296 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
297 */
298 struct efx_rx_queue {
299 struct efx_nic *efx;
300 int core_index;
301 struct efx_rx_buffer *buffer;
302 struct efx_special_buffer rxd;
303 unsigned int ptr_mask;
304 bool enabled;
305 bool flush_pending;
306
307 unsigned int added_count;
308 unsigned int notified_count;
309 unsigned int removed_count;
310 unsigned int scatter_n;
311 struct page **page_ring;
312 unsigned int page_add;
313 unsigned int page_remove;
314 unsigned int page_recycle_count;
315 unsigned int page_recycle_failed;
316 unsigned int page_recycle_full;
317 unsigned int page_ptr_mask;
318 unsigned int max_fill;
319 unsigned int fast_fill_trigger;
320 unsigned int min_fill;
321 unsigned int min_overfill;
322 unsigned int recycle_count;
323 struct timer_list slow_fill;
324 unsigned int slow_fill_count;
325 };
326
327 /**
328 * struct efx_buffer - An Efx general-purpose buffer
329 * @addr: host base address of the buffer
330 * @dma_addr: DMA base address of the buffer
331 * @len: Buffer length, in bytes
332 *
333 * The NIC uses these buffers for its interrupt status registers and
334 * MAC stats dumps.
335 */
336 struct efx_buffer {
337 void *addr;
338 dma_addr_t dma_addr;
339 unsigned int len;
340 };
341
342
343 enum efx_rx_alloc_method {
344 RX_ALLOC_METHOD_AUTO = 0,
345 RX_ALLOC_METHOD_SKB = 1,
346 RX_ALLOC_METHOD_PAGE = 2,
347 };
348
349 /**
350 * struct efx_channel - An Efx channel
351 *
352 * A channel comprises an event queue, at least one TX queue, at least
353 * one RX queue, and an associated tasklet for processing the event
354 * queue.
355 *
356 * @efx: Associated Efx NIC
357 * @channel: Channel instance number
358 * @type: Channel type definition
359 * @enabled: Channel enabled indicator
360 * @irq: IRQ number (MSI and MSI-X only)
361 * @irq_moderation: IRQ moderation value (in hardware ticks)
362 * @napi_dev: Net device used with NAPI
363 * @napi_str: NAPI control structure
364 * @work_pending: Is work pending via NAPI?
365 * @eventq: Event queue buffer
366 * @eventq_mask: Event queue pointer mask
367 * @eventq_read_ptr: Event queue read pointer
368 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
369 * @irq_count: Number of IRQs since last adaptive moderation decision
370 * @irq_mod_score: IRQ moderation score
371 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
372 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
373 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
374 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
375 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
376 * @n_rx_overlength: Count of RX_OVERLENGTH errors
377 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
378 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
379 * lack of descriptors
380 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by
381 * __efx_rx_packet(), or zero if there is none
382 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered
383 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0
384 * @rx_queue: RX queue for this channel
385 * @tx_queue: TX queues for this channel
386 */
387 struct efx_channel {
388 struct efx_nic *efx;
389 int channel;
390 const struct efx_channel_type *type;
391 bool enabled;
392 int irq;
393 unsigned int irq_moderation;
394 struct net_device *napi_dev;
395 struct napi_struct napi_str;
396 bool work_pending;
397 struct efx_special_buffer eventq;
398 unsigned int eventq_mask;
399 unsigned int eventq_read_ptr;
400 int event_test_cpu;
401
402 unsigned int irq_count;
403 unsigned int irq_mod_score;
404 #ifdef CONFIG_RFS_ACCEL
405 unsigned int rfs_filters_added;
406 #endif
407
408 unsigned n_rx_tobe_disc;
409 unsigned n_rx_ip_hdr_chksum_err;
410 unsigned n_rx_tcp_udp_chksum_err;
411 unsigned n_rx_mcast_mismatch;
412 unsigned n_rx_frm_trunc;
413 unsigned n_rx_overlength;
414 unsigned n_skbuff_leaks;
415 unsigned int n_rx_nodesc_trunc;
416
417 unsigned int rx_pkt_n_frags;
418 unsigned int rx_pkt_index;
419
420 struct efx_rx_queue rx_queue;
421 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES];
422 };
423
424 /**
425 * struct efx_channel_type - distinguishes traffic and extra channels
426 * @handle_no_channel: Handle failure to allocate an extra channel
427 * @pre_probe: Set up extra state prior to initialisation
428 * @post_remove: Tear down extra state after finalisation, if allocated.
429 * May be called on channels that have not been probed.
430 * @get_name: Generate the channel's name (used for its IRQ handler)
431 * @copy: Copy the channel state prior to reallocation. May be %NULL if
432 * reallocation is not supported.
433 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()
434 * @keep_eventq: Flag for whether event queue should be kept initialised
435 * while the device is stopped
436 */
437 struct efx_channel_type {
438 void (*handle_no_channel)(struct efx_nic *);
439 int (*pre_probe)(struct efx_channel *);
440 void (*post_remove)(struct efx_channel *);
441 void (*get_name)(struct efx_channel *, char *buf, size_t len);
442 struct efx_channel *(*copy)(const struct efx_channel *);
443 bool (*receive_skb)(struct efx_channel *, struct sk_buff *);
444 bool keep_eventq;
445 };
446
447 enum efx_led_mode {
448 EFX_LED_OFF = 0,
449 EFX_LED_ON = 1,
450 EFX_LED_DEFAULT = 2
451 };
452
453 #define STRING_TABLE_LOOKUP(val, member) \
454 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
455
456 extern const char *const efx_loopback_mode_names[];
457 extern const unsigned int efx_loopback_mode_max;
458 #define LOOPBACK_MODE(efx) \
459 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
460
461 extern const char *const efx_reset_type_names[];
462 extern const unsigned int efx_reset_type_max;
463 #define RESET_TYPE(type) \
464 STRING_TABLE_LOOKUP(type, efx_reset_type)
465
466 enum efx_int_mode {
467 /* Be careful if altering to correct macro below */
468 EFX_INT_MODE_MSIX = 0,
469 EFX_INT_MODE_MSI = 1,
470 EFX_INT_MODE_LEGACY = 2,
471 EFX_INT_MODE_MAX /* Insert any new items before this */
472 };
473 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
474
475 enum nic_state {
476 STATE_UNINIT = 0, /* device being probed/removed or is frozen */
477 STATE_READY = 1, /* hardware ready and netdev registered */
478 STATE_DISABLED = 2, /* device disabled due to hardware errors */
479 STATE_RECOVERY = 3, /* device recovering from PCI error */
480 };
481
482 /*
483 * Alignment of the skb->head which wraps a page-allocated RX buffer
484 *
485 * The skb allocated to wrap an rx_buffer can have this alignment. Since
486 * the data is memcpy'd from the rx_buf, it does not need to be equal to
487 * NET_IP_ALIGN.
488 */
489 #define EFX_PAGE_SKB_ALIGN 2
490
491 /* Forward declaration */
492 struct efx_nic;
493
494 /* Pseudo bit-mask flow control field */
495 #define EFX_FC_RX FLOW_CTRL_RX
496 #define EFX_FC_TX FLOW_CTRL_TX
497 #define EFX_FC_AUTO 4
498
499 /**
500 * struct efx_link_state - Current state of the link
501 * @up: Link is up
502 * @fd: Link is full-duplex
503 * @fc: Actual flow control flags
504 * @speed: Link speed (Mbps)
505 */
506 struct efx_link_state {
507 bool up;
508 bool fd;
509 u8 fc;
510 unsigned int speed;
511 };
512
efx_link_state_equal(const struct efx_link_state * left,const struct efx_link_state * right)513 static inline bool efx_link_state_equal(const struct efx_link_state *left,
514 const struct efx_link_state *right)
515 {
516 return left->up == right->up && left->fd == right->fd &&
517 left->fc == right->fc && left->speed == right->speed;
518 }
519
520 /**
521 * struct efx_phy_operations - Efx PHY operations table
522 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
523 * efx->loopback_modes.
524 * @init: Initialise PHY
525 * @fini: Shut down PHY
526 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
527 * @poll: Update @link_state and report whether it changed.
528 * Serialised by the mac_lock.
529 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
530 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
531 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
532 * (only needed where AN bit is set in mmds)
533 * @test_alive: Test that PHY is 'alive' (online)
534 * @test_name: Get the name of a PHY-specific test/result
535 * @run_tests: Run tests and record results as appropriate (offline).
536 * Flags are the ethtool tests flags.
537 */
538 struct efx_phy_operations {
539 int (*probe) (struct efx_nic *efx);
540 int (*init) (struct efx_nic *efx);
541 void (*fini) (struct efx_nic *efx);
542 void (*remove) (struct efx_nic *efx);
543 int (*reconfigure) (struct efx_nic *efx);
544 bool (*poll) (struct efx_nic *efx);
545 void (*get_settings) (struct efx_nic *efx,
546 struct ethtool_cmd *ecmd);
547 int (*set_settings) (struct efx_nic *efx,
548 struct ethtool_cmd *ecmd);
549 void (*set_npage_adv) (struct efx_nic *efx, u32);
550 int (*test_alive) (struct efx_nic *efx);
551 const char *(*test_name) (struct efx_nic *efx, unsigned int index);
552 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
553 int (*get_module_eeprom) (struct efx_nic *efx,
554 struct ethtool_eeprom *ee,
555 u8 *data);
556 int (*get_module_info) (struct efx_nic *efx,
557 struct ethtool_modinfo *modinfo);
558 };
559
560 /**
561 * enum efx_phy_mode - PHY operating mode flags
562 * @PHY_MODE_NORMAL: on and should pass traffic
563 * @PHY_MODE_TX_DISABLED: on with TX disabled
564 * @PHY_MODE_LOW_POWER: set to low power through MDIO
565 * @PHY_MODE_OFF: switched off through external control
566 * @PHY_MODE_SPECIAL: on but will not pass traffic
567 */
568 enum efx_phy_mode {
569 PHY_MODE_NORMAL = 0,
570 PHY_MODE_TX_DISABLED = 1,
571 PHY_MODE_LOW_POWER = 2,
572 PHY_MODE_OFF = 4,
573 PHY_MODE_SPECIAL = 8,
574 };
575
efx_phy_mode_disabled(enum efx_phy_mode mode)576 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
577 {
578 return !!(mode & ~PHY_MODE_TX_DISABLED);
579 }
580
581 /*
582 * Efx extended statistics
583 *
584 * Not all statistics are provided by all supported MACs. The purpose
585 * is this structure is to contain the raw statistics provided by each
586 * MAC.
587 */
588 struct efx_mac_stats {
589 u64 tx_bytes;
590 u64 tx_good_bytes;
591 u64 tx_bad_bytes;
592 u64 tx_packets;
593 u64 tx_bad;
594 u64 tx_pause;
595 u64 tx_control;
596 u64 tx_unicast;
597 u64 tx_multicast;
598 u64 tx_broadcast;
599 u64 tx_lt64;
600 u64 tx_64;
601 u64 tx_65_to_127;
602 u64 tx_128_to_255;
603 u64 tx_256_to_511;
604 u64 tx_512_to_1023;
605 u64 tx_1024_to_15xx;
606 u64 tx_15xx_to_jumbo;
607 u64 tx_gtjumbo;
608 u64 tx_collision;
609 u64 tx_single_collision;
610 u64 tx_multiple_collision;
611 u64 tx_excessive_collision;
612 u64 tx_deferred;
613 u64 tx_late_collision;
614 u64 tx_excessive_deferred;
615 u64 tx_non_tcpudp;
616 u64 tx_mac_src_error;
617 u64 tx_ip_src_error;
618 u64 rx_bytes;
619 u64 rx_good_bytes;
620 u64 rx_bad_bytes;
621 u64 rx_packets;
622 u64 rx_good;
623 u64 rx_bad;
624 u64 rx_pause;
625 u64 rx_control;
626 u64 rx_unicast;
627 u64 rx_multicast;
628 u64 rx_broadcast;
629 u64 rx_lt64;
630 u64 rx_64;
631 u64 rx_65_to_127;
632 u64 rx_128_to_255;
633 u64 rx_256_to_511;
634 u64 rx_512_to_1023;
635 u64 rx_1024_to_15xx;
636 u64 rx_15xx_to_jumbo;
637 u64 rx_gtjumbo;
638 u64 rx_bad_lt64;
639 u64 rx_bad_64_to_15xx;
640 u64 rx_bad_15xx_to_jumbo;
641 u64 rx_bad_gtjumbo;
642 u64 rx_overflow;
643 u64 rx_missed;
644 u64 rx_false_carrier;
645 u64 rx_symbol_error;
646 u64 rx_align_error;
647 u64 rx_length_error;
648 u64 rx_internal_error;
649 u64 rx_good_lt64;
650 };
651
652 /* Number of bits used in a multicast filter hash address */
653 #define EFX_MCAST_HASH_BITS 8
654
655 /* Number of (single-bit) entries in a multicast filter hash */
656 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
657
658 /* An Efx multicast filter hash */
659 union efx_multicast_hash {
660 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
661 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
662 };
663
664 struct efx_filter_state;
665 struct efx_vf;
666 struct vfdi_status;
667
668 /**
669 * struct efx_nic - an Efx NIC
670 * @name: Device name (net device name or bus id before net device registered)
671 * @pci_dev: The PCI device
672 * @type: Controller type attributes
673 * @legacy_irq: IRQ number
674 * @legacy_irq_enabled: Are IRQs enabled on NIC (INT_EN_KER register)?
675 * @workqueue: Workqueue for port reconfigures and the HW monitor.
676 * Work items do not hold and must not acquire RTNL.
677 * @workqueue_name: Name of workqueue
678 * @reset_work: Scheduled reset workitem
679 * @membase_phys: Memory BAR value as physical address
680 * @membase: Memory BAR value
681 * @interrupt_mode: Interrupt mode
682 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
683 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
684 * @irq_rx_moderation: IRQ moderation time for RX event queues
685 * @msg_enable: Log message enable flags
686 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.
687 * @reset_pending: Bitmask for pending resets
688 * @tx_queue: TX DMA queues
689 * @rx_queue: RX DMA queues
690 * @channel: Channels
691 * @channel_name: Names for channels and their IRQs
692 * @extra_channel_types: Types of extra (non-traffic) channels that
693 * should be allocated for this NIC
694 * @rxq_entries: Size of receive queues requested by user.
695 * @txq_entries: Size of transmit queues requested by user.
696 * @txq_stop_thresh: TX queue fill level at or above which we stop it.
697 * @txq_wake_thresh: TX queue fill level at or below which we wake it.
698 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
699 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
700 * @sram_lim_qw: Qword address limit of SRAM
701 * @next_buffer_table: First available buffer table id
702 * @n_channels: Number of channels in use
703 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
704 * @n_tx_channels: Number of channels used for TX
705 * @rx_dma_len: Current maximum RX DMA length
706 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
707 * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
708 * for use in sk_buff::truesize
709 * @rx_hash_key: Toeplitz hash key for RSS
710 * @rx_indir_table: Indirection table for RSS
711 * @rx_scatter: Scatter mode enabled for receives
712 * @int_error_count: Number of internal errors seen recently
713 * @int_error_expire: Time at which error count will be expired
714 * @irq_status: Interrupt status buffer
715 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
716 * @irq_level: IRQ level/index for IRQs not triggered by an event queue
717 * @selftest_work: Work item for asynchronous self-test
718 * @mtd_list: List of MTDs attached to the NIC
719 * @nic_data: Hardware dependent state
720 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
721 * efx_monitor() and efx_reconfigure_port()
722 * @port_enabled: Port enabled indicator.
723 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
724 * efx_mac_work() with kernel interfaces. Safe to read under any
725 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
726 * be held to modify it.
727 * @port_initialized: Port initialized?
728 * @net_dev: Operating system network device. Consider holding the rtnl lock
729 * @stats_buffer: DMA buffer for statistics
730 * @phy_type: PHY type
731 * @phy_op: PHY interface
732 * @phy_data: PHY private data (including PHY-specific stats)
733 * @mdio: PHY MDIO interface
734 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
735 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
736 * @link_advertising: Autonegotiation advertising flags
737 * @link_state: Current state of the link
738 * @n_link_state_changes: Number of times the link has changed state
739 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
740 * @multicast_hash: Multicast hash table
741 * @wanted_fc: Wanted flow control flags
742 * @fc_disable: When non-zero flow control is disabled. Typically used to
743 * ensure that network back pressure doesn't delay dma queue flushes.
744 * Serialised by the rtnl lock.
745 * @mac_work: Work item for changing MAC promiscuity and multicast hash
746 * @loopback_mode: Loopback status
747 * @loopback_modes: Supported loopback mode bitmask
748 * @loopback_selftest: Offline self-test private state
749 * @drain_pending: Count of RX and TX queues that haven't been flushed and drained.
750 * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
751 * Decremented when the efx_flush_rx_queue() is called.
752 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
753 * completed (either success or failure). Not used when MCDI is used to
754 * flush receive queues.
755 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
756 * @vf: Array of &struct efx_vf objects.
757 * @vf_count: Number of VFs intended to be enabled.
758 * @vf_init_count: Number of VFs that have been fully initialised.
759 * @vi_scale: log2 number of vnics per VF.
760 * @vf_buftbl_base: The zeroth buffer table index used to back VF queues.
761 * @vfdi_status: Common VFDI status page to be dmad to VF address space.
762 * @local_addr_list: List of local addresses. Protected by %local_lock.
763 * @local_page_list: List of DMA addressable pages used to broadcast
764 * %local_addr_list. Protected by %local_lock.
765 * @local_lock: Mutex protecting %local_addr_list and %local_page_list.
766 * @peer_work: Work item to broadcast peer addresses to VMs.
767 * @ptp_data: PTP state data
768 * @monitor_work: Hardware monitor workitem
769 * @biu_lock: BIU (bus interface unit) lock
770 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This
771 * field is used by efx_test_interrupts() to verify that an
772 * interrupt has occurred.
773 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
774 * @mac_stats: MAC statistics. These include all statistics the MACs
775 * can provide. Generic code converts these into a standard
776 * &struct net_device_stats.
777 * @stats_lock: Statistics update lock. Serialises statistics fetches
778 * and access to @mac_stats.
779 *
780 * This is stored in the private area of the &struct net_device.
781 */
782 struct efx_nic {
783 /* The following fields should be written very rarely */
784
785 char name[IFNAMSIZ];
786 struct pci_dev *pci_dev;
787 const struct efx_nic_type *type;
788 int legacy_irq;
789 bool legacy_irq_enabled;
790 struct workqueue_struct *workqueue;
791 char workqueue_name[16];
792 struct work_struct reset_work;
793 resource_size_t membase_phys;
794 void __iomem *membase;
795
796 enum efx_int_mode interrupt_mode;
797 unsigned int timer_quantum_ns;
798 bool irq_rx_adaptive;
799 unsigned int irq_rx_moderation;
800 u32 msg_enable;
801
802 enum nic_state state;
803 unsigned long reset_pending;
804
805 struct efx_channel *channel[EFX_MAX_CHANNELS];
806 char channel_name[EFX_MAX_CHANNELS][IFNAMSIZ + 6];
807 const struct efx_channel_type *
808 extra_channel_type[EFX_MAX_EXTRA_CHANNELS];
809
810 unsigned rxq_entries;
811 unsigned txq_entries;
812 unsigned int txq_stop_thresh;
813 unsigned int txq_wake_thresh;
814
815 unsigned tx_dc_base;
816 unsigned rx_dc_base;
817 unsigned sram_lim_qw;
818 unsigned next_buffer_table;
819 unsigned n_channels;
820 unsigned n_rx_channels;
821 unsigned rss_spread;
822 unsigned tx_channel_offset;
823 unsigned n_tx_channels;
824 unsigned int rx_dma_len;
825 unsigned int rx_buffer_order;
826 unsigned int rx_buffer_truesize;
827 unsigned int rx_page_buf_step;
828 unsigned int rx_bufs_per_page;
829 unsigned int rx_pages_per_batch;
830 u8 rx_hash_key[40];
831 u32 rx_indir_table[128];
832 bool rx_scatter;
833
834 unsigned int_error_count;
835 unsigned long int_error_expire;
836
837 struct efx_buffer irq_status;
838 unsigned irq_zero_count;
839 unsigned irq_level;
840 struct delayed_work selftest_work;
841
842 #ifdef CONFIG_SFC_MTD
843 struct list_head mtd_list;
844 #endif
845
846 void *nic_data;
847
848 struct mutex mac_lock;
849 struct work_struct mac_work;
850 bool port_enabled;
851
852 bool port_initialized;
853 struct net_device *net_dev;
854
855 struct efx_buffer stats_buffer;
856
857 unsigned int phy_type;
858 const struct efx_phy_operations *phy_op;
859 void *phy_data;
860 struct mdio_if_info mdio;
861 unsigned int mdio_bus;
862 enum efx_phy_mode phy_mode;
863
864 u32 link_advertising;
865 struct efx_link_state link_state;
866 unsigned int n_link_state_changes;
867
868 bool promiscuous;
869 union efx_multicast_hash multicast_hash;
870 u8 wanted_fc;
871 unsigned fc_disable;
872
873 atomic_t rx_reset;
874 enum efx_loopback_mode loopback_mode;
875 u64 loopback_modes;
876
877 void *loopback_selftest;
878
879 struct efx_filter_state *filter_state;
880
881 atomic_t drain_pending;
882 atomic_t rxq_flush_pending;
883 atomic_t rxq_flush_outstanding;
884 wait_queue_head_t flush_wq;
885
886 #ifdef CONFIG_SFC_SRIOV
887 struct efx_channel *vfdi_channel;
888 struct efx_vf *vf;
889 unsigned vf_count;
890 unsigned vf_init_count;
891 unsigned vi_scale;
892 unsigned vf_buftbl_base;
893 struct efx_buffer vfdi_status;
894 struct list_head local_addr_list;
895 struct list_head local_page_list;
896 struct mutex local_lock;
897 struct work_struct peer_work;
898 #endif
899
900 struct efx_ptp_data *ptp_data;
901
902 /* The following fields may be written more often */
903
904 struct delayed_work monitor_work ____cacheline_aligned_in_smp;
905 spinlock_t biu_lock;
906 int last_irq_cpu;
907 unsigned n_rx_nodesc_drop_cnt;
908 struct efx_mac_stats mac_stats;
909 spinlock_t stats_lock;
910 };
911
efx_dev_registered(struct efx_nic * efx)912 static inline int efx_dev_registered(struct efx_nic *efx)
913 {
914 return efx->net_dev->reg_state == NETREG_REGISTERED;
915 }
916
efx_port_num(struct efx_nic * efx)917 static inline unsigned int efx_port_num(struct efx_nic *efx)
918 {
919 return efx->net_dev->dev_id;
920 }
921
922 /**
923 * struct efx_nic_type - Efx device type definition
924 * @probe: Probe the controller
925 * @remove: Free resources allocated by probe()
926 * @init: Initialise the controller
927 * @dimension_resources: Dimension controller resources (buffer table,
928 * and VIs once the available interrupt resources are clear)
929 * @fini: Shut down the controller
930 * @monitor: Periodic function for polling link state and hardware monitor
931 * @map_reset_reason: Map ethtool reset reason to a reset method
932 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
933 * @reset: Reset the controller hardware and possibly the PHY. This will
934 * be called while the controller is uninitialised.
935 * @probe_port: Probe the MAC and PHY
936 * @remove_port: Free resources allocated by probe_port()
937 * @handle_global_event: Handle a "global" event (may be %NULL)
938 * @prepare_flush: Prepare the hardware for flushing the DMA queues
939 * @finish_flush: Clean up after flushing the DMA queues
940 * @update_stats: Update statistics not provided by event handling
941 * @start_stats: Start the regular fetching of statistics
942 * @stop_stats: Stop the regular fetching of statistics
943 * @set_id_led: Set state of identifying LED or revert to automatic function
944 * @push_irq_moderation: Apply interrupt moderation value
945 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
946 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
947 * to the hardware. Serialised by the mac_lock.
948 * @check_mac_fault: Check MAC fault state. True if fault present.
949 * @get_wol: Get WoL configuration from driver state
950 * @set_wol: Push WoL configuration to the NIC
951 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
952 * @test_chip: Test registers. Should use efx_nic_test_registers(), and is
953 * expected to reset the NIC.
954 * @test_nvram: Test validity of NVRAM contents
955 * @revision: Hardware architecture revision
956 * @mem_map_size: Memory BAR mapped size
957 * @txd_ptr_tbl_base: TX descriptor ring base address
958 * @rxd_ptr_tbl_base: RX descriptor ring base address
959 * @buf_tbl_base: Buffer table base address
960 * @evq_ptr_tbl_base: Event queue pointer table base address
961 * @evq_rptr_tbl_base: Event queue read-pointer table base address
962 * @max_dma_mask: Maximum possible DMA mask
963 * @rx_buffer_hash_size: Size of hash at start of RX packet
964 * @rx_buffer_padding: Size of padding at end of RX packet
965 * @can_rx_scatter: NIC is able to scatter packet to multiple buffers
966 * @max_interrupt_mode: Highest capability interrupt mode supported
967 * from &enum efx_init_mode.
968 * @phys_addr_channels: Number of channels with physically addressed
969 * descriptors
970 * @timer_period_max: Maximum period of interrupt timer (in ticks)
971 * @offload_features: net_device feature flags for protocol offload
972 * features implemented in hardware
973 */
974 struct efx_nic_type {
975 int (*probe)(struct efx_nic *efx);
976 void (*remove)(struct efx_nic *efx);
977 int (*init)(struct efx_nic *efx);
978 void (*dimension_resources)(struct efx_nic *efx);
979 void (*fini)(struct efx_nic *efx);
980 void (*monitor)(struct efx_nic *efx);
981 enum reset_type (*map_reset_reason)(enum reset_type reason);
982 int (*map_reset_flags)(u32 *flags);
983 int (*reset)(struct efx_nic *efx, enum reset_type method);
984 int (*probe_port)(struct efx_nic *efx);
985 void (*remove_port)(struct efx_nic *efx);
986 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
987 void (*prepare_flush)(struct efx_nic *efx);
988 void (*finish_flush)(struct efx_nic *efx);
989 void (*update_stats)(struct efx_nic *efx);
990 void (*start_stats)(struct efx_nic *efx);
991 void (*stop_stats)(struct efx_nic *efx);
992 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
993 void (*push_irq_moderation)(struct efx_channel *channel);
994 int (*reconfigure_port)(struct efx_nic *efx);
995 int (*reconfigure_mac)(struct efx_nic *efx);
996 bool (*check_mac_fault)(struct efx_nic *efx);
997 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
998 int (*set_wol)(struct efx_nic *efx, u32 type);
999 void (*resume_wol)(struct efx_nic *efx);
1000 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests);
1001 int (*test_nvram)(struct efx_nic *efx);
1002
1003 int revision;
1004 unsigned int mem_map_size;
1005 unsigned int txd_ptr_tbl_base;
1006 unsigned int rxd_ptr_tbl_base;
1007 unsigned int buf_tbl_base;
1008 unsigned int evq_ptr_tbl_base;
1009 unsigned int evq_rptr_tbl_base;
1010 u64 max_dma_mask;
1011 unsigned int rx_buffer_hash_size;
1012 unsigned int rx_buffer_padding;
1013 bool can_rx_scatter;
1014 unsigned int max_interrupt_mode;
1015 unsigned int phys_addr_channels;
1016 unsigned int timer_period_max;
1017 netdev_features_t offload_features;
1018 };
1019
1020 /**************************************************************************
1021 *
1022 * Prototypes and inline functions
1023 *
1024 *************************************************************************/
1025
1026 static inline struct efx_channel *
efx_get_channel(struct efx_nic * efx,unsigned index)1027 efx_get_channel(struct efx_nic *efx, unsigned index)
1028 {
1029 EFX_BUG_ON_PARANOID(index >= efx->n_channels);
1030 return efx->channel[index];
1031 }
1032
1033 /* Iterate over all used channels */
1034 #define efx_for_each_channel(_channel, _efx) \
1035 for (_channel = (_efx)->channel[0]; \
1036 _channel; \
1037 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
1038 (_efx)->channel[_channel->channel + 1] : NULL)
1039
1040 /* Iterate over all used channels in reverse */
1041 #define efx_for_each_channel_rev(_channel, _efx) \
1042 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \
1043 _channel; \
1044 _channel = _channel->channel ? \
1045 (_efx)->channel[_channel->channel - 1] : NULL)
1046
1047 static inline struct efx_tx_queue *
efx_get_tx_queue(struct efx_nic * efx,unsigned index,unsigned type)1048 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type)
1049 {
1050 EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels ||
1051 type >= EFX_TXQ_TYPES);
1052 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type];
1053 }
1054
efx_channel_has_tx_queues(struct efx_channel * channel)1055 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel)
1056 {
1057 return channel->channel - channel->efx->tx_channel_offset <
1058 channel->efx->n_tx_channels;
1059 }
1060
1061 static inline struct efx_tx_queue *
efx_channel_get_tx_queue(struct efx_channel * channel,unsigned type)1062 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type)
1063 {
1064 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) ||
1065 type >= EFX_TXQ_TYPES);
1066 return &channel->tx_queue[type];
1067 }
1068
efx_tx_queue_used(struct efx_tx_queue * tx_queue)1069 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue)
1070 {
1071 return !(tx_queue->efx->net_dev->num_tc < 2 &&
1072 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI);
1073 }
1074
1075 /* Iterate over all TX queues belonging to a channel */
1076 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
1077 if (!efx_channel_has_tx_queues(_channel)) \
1078 ; \
1079 else \
1080 for (_tx_queue = (_channel)->tx_queue; \
1081 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \
1082 efx_tx_queue_used(_tx_queue); \
1083 _tx_queue++)
1084
1085 /* Iterate over all possible TX queues belonging to a channel */
1086 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \
1087 if (!efx_channel_has_tx_queues(_channel)) \
1088 ; \
1089 else \
1090 for (_tx_queue = (_channel)->tx_queue; \
1091 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
1092 _tx_queue++)
1093
efx_channel_has_rx_queue(struct efx_channel * channel)1094 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel)
1095 {
1096 return channel->rx_queue.core_index >= 0;
1097 }
1098
1099 static inline struct efx_rx_queue *
efx_channel_get_rx_queue(struct efx_channel * channel)1100 efx_channel_get_rx_queue(struct efx_channel *channel)
1101 {
1102 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel));
1103 return &channel->rx_queue;
1104 }
1105
1106 /* Iterate over all RX queues belonging to a channel */
1107 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
1108 if (!efx_channel_has_rx_queue(_channel)) \
1109 ; \
1110 else \
1111 for (_rx_queue = &(_channel)->rx_queue; \
1112 _rx_queue; \
1113 _rx_queue = NULL)
1114
1115 static inline struct efx_channel *
efx_rx_queue_channel(struct efx_rx_queue * rx_queue)1116 efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
1117 {
1118 return container_of(rx_queue, struct efx_channel, rx_queue);
1119 }
1120
efx_rx_queue_index(struct efx_rx_queue * rx_queue)1121 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
1122 {
1123 return efx_rx_queue_channel(rx_queue)->channel;
1124 }
1125
1126 /* Returns a pointer to the specified receive buffer in the RX
1127 * descriptor queue.
1128 */
efx_rx_buffer(struct efx_rx_queue * rx_queue,unsigned int index)1129 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
1130 unsigned int index)
1131 {
1132 return &rx_queue->buffer[index];
1133 }
1134
1135
1136 /**
1137 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1138 *
1139 * This calculates the maximum frame length that will be used for a
1140 * given MTU. The frame length will be equal to the MTU plus a
1141 * constant amount of header space and padding. This is the quantity
1142 * that the net driver will program into the MAC as the maximum frame
1143 * length.
1144 *
1145 * The 10G MAC requires 8-byte alignment on the frame
1146 * length, so we round up to the nearest 8.
1147 *
1148 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1149 * XGMII cycle). If the frame length reaches the maximum value in the
1150 * same cycle, the XMAC can miss the IPG altogether. We work around
1151 * this by adding a further 16 bytes.
1152 */
1153 #define EFX_MAX_FRAME_LEN(mtu) \
1154 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
1155
efx_xmit_with_hwtstamp(struct sk_buff * skb)1156 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb)
1157 {
1158 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
1159 }
efx_xmit_hwtstamp_pending(struct sk_buff * skb)1160 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb)
1161 {
1162 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1163 }
1164
1165 #endif /* EFX_NET_DRIVER_H */
1166