1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/sched.h>
30 #include <linux/wait.h>
31 #include <linux/gfp.h>
32
33 #include "iwl-prph.h"
34 #include "iwl-io.h"
35 #include "internal.h"
36 #include "iwl-op-mode.h"
37
38 /******************************************************************************
39 *
40 * RX path functions
41 *
42 ******************************************************************************/
43
44 /*
45 * Rx theory of operation
46 *
47 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
48 * each of which point to Receive Buffers to be filled by the NIC. These get
49 * used not only for Rx frames, but for any command response or notification
50 * from the NIC. The driver and NIC manage the Rx buffers by means
51 * of indexes into the circular buffer.
52 *
53 * Rx Queue Indexes
54 * The host/firmware share two index registers for managing the Rx buffers.
55 *
56 * The READ index maps to the first position that the firmware may be writing
57 * to -- the driver can read up to (but not including) this position and get
58 * good data.
59 * The READ index is managed by the firmware once the card is enabled.
60 *
61 * The WRITE index maps to the last position the driver has read from -- the
62 * position preceding WRITE is the last slot the firmware can place a packet.
63 *
64 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
65 * WRITE = READ.
66 *
67 * During initialization, the host sets up the READ queue position to the first
68 * INDEX position, and WRITE to the last (READ - 1 wrapped)
69 *
70 * When the firmware places a packet in a buffer, it will advance the READ index
71 * and fire the RX interrupt. The driver can then query the READ index and
72 * process as many packets as possible, moving the WRITE index forward as it
73 * resets the Rx queue buffers with new memory.
74 *
75 * The management in the driver is as follows:
76 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
77 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
78 * to replenish the iwl->rxq->rx_free.
79 * + In iwl_pcie_rx_replenish (scheduled) if 'processed' != 'read' then the
80 * iwl->rxq is replenished and the READ INDEX is updated (updating the
81 * 'processed' and 'read' driver indexes as well)
82 * + A received packet is processed and handed to the kernel network stack,
83 * detached from the iwl->rxq. The driver 'processed' index is updated.
84 * + The Host/Firmware iwl->rxq is replenished at irq thread time from the
85 * rx_free list. If there are no allocated buffers in iwl->rxq->rx_free,
86 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
87 * If there were enough free buffers and RX_STALLED is set it is cleared.
88 *
89 *
90 * Driver sequence:
91 *
92 * iwl_rxq_alloc() Allocates rx_free
93 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls
94 * iwl_pcie_rxq_restock
95 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx
96 * queue, updates firmware pointers, and updates
97 * the WRITE index. If insufficient rx_free buffers
98 * are available, schedules iwl_pcie_rx_replenish
99 *
100 * -- enable interrupts --
101 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
102 * READ INDEX, detaching the SKB from the pool.
103 * Moves the packet buffer from queue to rx_used.
104 * Calls iwl_pcie_rxq_restock to refill any empty
105 * slots.
106 * ...
107 *
108 */
109
110 /*
111 * iwl_rxq_space - Return number of free slots available in queue.
112 */
iwl_rxq_space(const struct iwl_rxq * q)113 static int iwl_rxq_space(const struct iwl_rxq *q)
114 {
115 int s = q->read - q->write;
116 if (s <= 0)
117 s += RX_QUEUE_SIZE;
118 /* keep some buffer to not confuse full and empty queue */
119 s -= 2;
120 if (s < 0)
121 s = 0;
122 return s;
123 }
124
125 /*
126 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
127 */
iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)128 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
129 {
130 return cpu_to_le32((u32)(dma_addr >> 8));
131 }
132
133 /*
134 * iwl_pcie_rx_stop - stops the Rx DMA
135 */
iwl_pcie_rx_stop(struct iwl_trans * trans)136 int iwl_pcie_rx_stop(struct iwl_trans *trans)
137 {
138 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
139 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
140 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
141 }
142
143 /*
144 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
145 */
iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans * trans,struct iwl_rxq * q)146 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_rxq *q)
147 {
148 unsigned long flags;
149 u32 reg;
150
151 spin_lock_irqsave(&q->lock, flags);
152
153 if (q->need_update == 0)
154 goto exit_unlock;
155
156 if (trans->cfg->base_params->shadow_reg_enable) {
157 /* shadow register enabled */
158 /* Device expects a multiple of 8 */
159 q->write_actual = (q->write & ~0x7);
160 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
161 } else {
162 struct iwl_trans_pcie *trans_pcie =
163 IWL_TRANS_GET_PCIE_TRANS(trans);
164
165 /* If power-saving is in use, make sure device is awake */
166 if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) {
167 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
168
169 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
170 IWL_DEBUG_INFO(trans,
171 "Rx queue requesting wakeup,"
172 " GP1 = 0x%x\n", reg);
173 iwl_set_bit(trans, CSR_GP_CNTRL,
174 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
175 goto exit_unlock;
176 }
177
178 q->write_actual = (q->write & ~0x7);
179 iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
180 q->write_actual);
181
182 /* Else device is assumed to be awake */
183 } else {
184 /* Device expects a multiple of 8 */
185 q->write_actual = (q->write & ~0x7);
186 iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
187 q->write_actual);
188 }
189 }
190 q->need_update = 0;
191
192 exit_unlock:
193 spin_unlock_irqrestore(&q->lock, flags);
194 }
195
196 /*
197 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
198 *
199 * If there are slots in the RX queue that need to be restocked,
200 * and we have free pre-allocated buffers, fill the ranks as much
201 * as we can, pulling from rx_free.
202 *
203 * This moves the 'write' index forward to catch up with 'processed', and
204 * also updates the memory address in the firmware to reference the new
205 * target buffer.
206 */
iwl_pcie_rxq_restock(struct iwl_trans * trans)207 static void iwl_pcie_rxq_restock(struct iwl_trans *trans)
208 {
209 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
210 struct iwl_rxq *rxq = &trans_pcie->rxq;
211 struct iwl_rx_mem_buffer *rxb;
212 unsigned long flags;
213
214 /*
215 * If the device isn't enabled - not need to try to add buffers...
216 * This can happen when we stop the device and still have an interrupt
217 * pending. We stop the APM before we sync the interrupts because we
218 * have to (see comment there). On the other hand, since the APM is
219 * stopped, we cannot access the HW (in particular not prph).
220 * So don't try to restock if the APM has been already stopped.
221 */
222 if (!test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status))
223 return;
224
225 spin_lock_irqsave(&rxq->lock, flags);
226 while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
227 /* The overwritten rxb must be a used one */
228 rxb = rxq->queue[rxq->write];
229 BUG_ON(rxb && rxb->page);
230
231 /* Get next free Rx buffer, remove from free list */
232 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
233 list);
234 list_del(&rxb->list);
235
236 /* Point to Rx buffer via next RBD in circular buffer */
237 rxq->bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
238 rxq->queue[rxq->write] = rxb;
239 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
240 rxq->free_count--;
241 }
242 spin_unlock_irqrestore(&rxq->lock, flags);
243 /* If the pre-allocated buffer pool is dropping low, schedule to
244 * refill it */
245 if (rxq->free_count <= RX_LOW_WATERMARK)
246 schedule_work(&trans_pcie->rx_replenish);
247
248 /* If we've added more space for the firmware to place data, tell it.
249 * Increment device's write pointer in multiples of 8. */
250 if (rxq->write_actual != (rxq->write & ~0x7)) {
251 spin_lock_irqsave(&rxq->lock, flags);
252 rxq->need_update = 1;
253 spin_unlock_irqrestore(&rxq->lock, flags);
254 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
255 }
256 }
257
258 /*
259 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
260 *
261 * A used RBD is an Rx buffer that has been given to the stack. To use it again
262 * a page must be allocated and the RBD must point to the page. This function
263 * doesn't change the HW pointer but handles the list of pages that is used by
264 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
265 * allocated buffers.
266 */
iwl_pcie_rxq_alloc_rbs(struct iwl_trans * trans,gfp_t priority)267 static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority)
268 {
269 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
270 struct iwl_rxq *rxq = &trans_pcie->rxq;
271 struct iwl_rx_mem_buffer *rxb;
272 struct page *page;
273 unsigned long flags;
274 gfp_t gfp_mask = priority;
275
276 while (1) {
277 spin_lock_irqsave(&rxq->lock, flags);
278 if (list_empty(&rxq->rx_used)) {
279 spin_unlock_irqrestore(&rxq->lock, flags);
280 return;
281 }
282 spin_unlock_irqrestore(&rxq->lock, flags);
283
284 if (rxq->free_count > RX_LOW_WATERMARK)
285 gfp_mask |= __GFP_NOWARN;
286
287 if (trans_pcie->rx_page_order > 0)
288 gfp_mask |= __GFP_COMP;
289
290 /* Alloc a new receive buffer */
291 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
292 if (!page) {
293 if (net_ratelimit())
294 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
295 "order: %d\n",
296 trans_pcie->rx_page_order);
297
298 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
299 net_ratelimit())
300 IWL_CRIT(trans, "Failed to alloc_pages with %s."
301 "Only %u free buffers remaining.\n",
302 priority == GFP_ATOMIC ?
303 "GFP_ATOMIC" : "GFP_KERNEL",
304 rxq->free_count);
305 /* We don't reschedule replenish work here -- we will
306 * call the restock method and if it still needs
307 * more buffers it will schedule replenish */
308 return;
309 }
310
311 spin_lock_irqsave(&rxq->lock, flags);
312
313 if (list_empty(&rxq->rx_used)) {
314 spin_unlock_irqrestore(&rxq->lock, flags);
315 __free_pages(page, trans_pcie->rx_page_order);
316 return;
317 }
318 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
319 list);
320 list_del(&rxb->list);
321 spin_unlock_irqrestore(&rxq->lock, flags);
322
323 BUG_ON(rxb->page);
324 rxb->page = page;
325 /* Get physical address of the RB */
326 rxb->page_dma =
327 dma_map_page(trans->dev, page, 0,
328 PAGE_SIZE << trans_pcie->rx_page_order,
329 DMA_FROM_DEVICE);
330 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
331 rxb->page = NULL;
332 spin_lock_irqsave(&rxq->lock, flags);
333 list_add(&rxb->list, &rxq->rx_used);
334 spin_unlock_irqrestore(&rxq->lock, flags);
335 __free_pages(page, trans_pcie->rx_page_order);
336 return;
337 }
338 /* dma address must be no more than 36 bits */
339 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
340 /* and also 256 byte aligned! */
341 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
342
343 spin_lock_irqsave(&rxq->lock, flags);
344
345 list_add_tail(&rxb->list, &rxq->rx_free);
346 rxq->free_count++;
347
348 spin_unlock_irqrestore(&rxq->lock, flags);
349 }
350 }
351
iwl_pcie_rxq_free_rbs(struct iwl_trans * trans)352 static void iwl_pcie_rxq_free_rbs(struct iwl_trans *trans)
353 {
354 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
355 struct iwl_rxq *rxq = &trans_pcie->rxq;
356 int i;
357
358 /* Fill the rx_used queue with _all_ of the Rx buffers */
359 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
360 /* In the reset function, these buffers may have been allocated
361 * to an SKB, so we need to unmap and free potential storage */
362 if (rxq->pool[i].page != NULL) {
363 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
364 PAGE_SIZE << trans_pcie->rx_page_order,
365 DMA_FROM_DEVICE);
366 __free_pages(rxq->pool[i].page,
367 trans_pcie->rx_page_order);
368 rxq->pool[i].page = NULL;
369 }
370 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
371 }
372 }
373
374 /*
375 * iwl_pcie_rx_replenish - Move all used buffers from rx_used to rx_free
376 *
377 * When moving to rx_free an page is allocated for the slot.
378 *
379 * Also restock the Rx queue via iwl_pcie_rxq_restock.
380 * This is called as a scheduled work item (except for during initialization)
381 */
iwl_pcie_rx_replenish(struct iwl_trans * trans)382 static void iwl_pcie_rx_replenish(struct iwl_trans *trans)
383 {
384 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
385 unsigned long flags;
386
387 iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL);
388
389 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
390 iwl_pcie_rxq_restock(trans);
391 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
392 }
393
iwl_pcie_rx_replenish_now(struct iwl_trans * trans)394 static void iwl_pcie_rx_replenish_now(struct iwl_trans *trans)
395 {
396 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC);
397
398 iwl_pcie_rxq_restock(trans);
399 }
400
iwl_pcie_rx_replenish_work(struct work_struct * data)401 static void iwl_pcie_rx_replenish_work(struct work_struct *data)
402 {
403 struct iwl_trans_pcie *trans_pcie =
404 container_of(data, struct iwl_trans_pcie, rx_replenish);
405
406 iwl_pcie_rx_replenish(trans_pcie->trans);
407 }
408
iwl_pcie_rx_alloc(struct iwl_trans * trans)409 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
410 {
411 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
412 struct iwl_rxq *rxq = &trans_pcie->rxq;
413 struct device *dev = trans->dev;
414
415 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
416
417 spin_lock_init(&rxq->lock);
418
419 if (WARN_ON(rxq->bd || rxq->rb_stts))
420 return -EINVAL;
421
422 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
423 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
424 &rxq->bd_dma, GFP_KERNEL);
425 if (!rxq->bd)
426 goto err_bd;
427
428 /*Allocate the driver's pointer to receive buffer status */
429 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
430 &rxq->rb_stts_dma, GFP_KERNEL);
431 if (!rxq->rb_stts)
432 goto err_rb_stts;
433
434 return 0;
435
436 err_rb_stts:
437 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
438 rxq->bd, rxq->bd_dma);
439 rxq->bd_dma = 0;
440 rxq->bd = NULL;
441 err_bd:
442 return -ENOMEM;
443 }
444
iwl_pcie_rx_hw_init(struct iwl_trans * trans,struct iwl_rxq * rxq)445 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
446 {
447 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
448 u32 rb_size;
449 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
450
451 if (trans_pcie->rx_buf_size_8k)
452 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
453 else
454 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
455
456 /* Stop Rx DMA */
457 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
458 /* reset and flush pointers */
459 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
460 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
461 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
462
463 /* Reset driver's Rx queue write index */
464 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
465
466 /* Tell device where to find RBD circular buffer in DRAM */
467 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
468 (u32)(rxq->bd_dma >> 8));
469
470 /* Tell device where in DRAM to update its Rx status */
471 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
472 rxq->rb_stts_dma >> 4);
473
474 /* Enable Rx DMA
475 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
476 * the credit mechanism in 5000 HW RX FIFO
477 * Direct rx interrupts to hosts
478 * Rx buffer size 4 or 8k
479 * RB timeout 0x10
480 * 256 RBDs
481 */
482 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
483 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
484 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
485 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
486 rb_size|
487 (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
488 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
489
490 /* Set interrupt coalescing timer to default (2048 usecs) */
491 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
492 }
493
iwl_pcie_rx_init(struct iwl_trans * trans)494 int iwl_pcie_rx_init(struct iwl_trans *trans)
495 {
496 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
497 struct iwl_rxq *rxq = &trans_pcie->rxq;
498 int i, err;
499 unsigned long flags;
500
501 if (!rxq->bd) {
502 err = iwl_pcie_rx_alloc(trans);
503 if (err)
504 return err;
505 }
506
507 spin_lock_irqsave(&rxq->lock, flags);
508 INIT_LIST_HEAD(&rxq->rx_free);
509 INIT_LIST_HEAD(&rxq->rx_used);
510
511 INIT_WORK(&trans_pcie->rx_replenish,
512 iwl_pcie_rx_replenish_work);
513
514 iwl_pcie_rxq_free_rbs(trans);
515
516 for (i = 0; i < RX_QUEUE_SIZE; i++)
517 rxq->queue[i] = NULL;
518
519 /* Set us so that we have processed and used all buffers, but have
520 * not restocked the Rx queue with fresh buffers */
521 rxq->read = rxq->write = 0;
522 rxq->write_actual = 0;
523 rxq->free_count = 0;
524 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
525 spin_unlock_irqrestore(&rxq->lock, flags);
526
527 iwl_pcie_rx_replenish(trans);
528
529 iwl_pcie_rx_hw_init(trans, rxq);
530
531 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
532 rxq->need_update = 1;
533 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
534 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
535
536 return 0;
537 }
538
iwl_pcie_rx_free(struct iwl_trans * trans)539 void iwl_pcie_rx_free(struct iwl_trans *trans)
540 {
541 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
542 struct iwl_rxq *rxq = &trans_pcie->rxq;
543 unsigned long flags;
544
545 /*if rxq->bd is NULL, it means that nothing has been allocated,
546 * exit now */
547 if (!rxq->bd) {
548 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
549 return;
550 }
551
552 cancel_work_sync(&trans_pcie->rx_replenish);
553
554 spin_lock_irqsave(&rxq->lock, flags);
555 iwl_pcie_rxq_free_rbs(trans);
556 spin_unlock_irqrestore(&rxq->lock, flags);
557
558 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
559 rxq->bd, rxq->bd_dma);
560 rxq->bd_dma = 0;
561 rxq->bd = NULL;
562
563 if (rxq->rb_stts)
564 dma_free_coherent(trans->dev,
565 sizeof(struct iwl_rb_status),
566 rxq->rb_stts, rxq->rb_stts_dma);
567 else
568 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
569 rxq->rb_stts_dma = 0;
570 rxq->rb_stts = NULL;
571 }
572
iwl_pcie_rx_handle_rb(struct iwl_trans * trans,struct iwl_rx_mem_buffer * rxb)573 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
574 struct iwl_rx_mem_buffer *rxb)
575 {
576 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
577 struct iwl_rxq *rxq = &trans_pcie->rxq;
578 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
579 unsigned long flags;
580 bool page_stolen = false;
581 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
582 u32 offset = 0;
583
584 if (WARN_ON(!rxb))
585 return;
586
587 dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
588
589 while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
590 struct iwl_rx_packet *pkt;
591 struct iwl_device_cmd *cmd;
592 u16 sequence;
593 bool reclaim;
594 int index, cmd_index, err, len;
595 struct iwl_rx_cmd_buffer rxcb = {
596 ._offset = offset,
597 ._rx_page_order = trans_pcie->rx_page_order,
598 ._page = rxb->page,
599 ._page_stolen = false,
600 .truesize = max_len,
601 };
602
603 pkt = rxb_addr(&rxcb);
604
605 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID))
606 break;
607
608 IWL_DEBUG_RX(trans, "cmd at offset %d: %s (0x%.2x)\n",
609 rxcb._offset, get_cmd_string(trans_pcie, pkt->hdr.cmd),
610 pkt->hdr.cmd);
611
612 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
613 len += sizeof(u32); /* account for status word */
614 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
615 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
616
617 /* Reclaim a command buffer only if this packet is a response
618 * to a (driver-originated) command.
619 * If the packet (e.g. Rx frame) originated from uCode,
620 * there is no command buffer to reclaim.
621 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
622 * but apparently a few don't get set; catch them here. */
623 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
624 if (reclaim) {
625 int i;
626
627 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
628 if (trans_pcie->no_reclaim_cmds[i] ==
629 pkt->hdr.cmd) {
630 reclaim = false;
631 break;
632 }
633 }
634 }
635
636 sequence = le16_to_cpu(pkt->hdr.sequence);
637 index = SEQ_TO_INDEX(sequence);
638 cmd_index = get_cmd_index(&txq->q, index);
639
640 if (reclaim)
641 cmd = txq->entries[cmd_index].cmd;
642 else
643 cmd = NULL;
644
645 err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
646
647 if (reclaim) {
648 kfree(txq->entries[cmd_index].free_buf);
649 txq->entries[cmd_index].free_buf = NULL;
650 }
651
652 /*
653 * After here, we should always check rxcb._page_stolen,
654 * if it is true then one of the handlers took the page.
655 */
656
657 if (reclaim) {
658 /* Invoke any callbacks, transfer the buffer to caller,
659 * and fire off the (possibly) blocking
660 * iwl_trans_send_cmd()
661 * as we reclaim the driver command queue */
662 if (!rxcb._page_stolen)
663 iwl_pcie_hcmd_complete(trans, &rxcb, err);
664 else
665 IWL_WARN(trans, "Claim null rxb?\n");
666 }
667
668 page_stolen |= rxcb._page_stolen;
669 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
670 }
671
672 /* page was stolen from us -- free our reference */
673 if (page_stolen) {
674 __free_pages(rxb->page, trans_pcie->rx_page_order);
675 rxb->page = NULL;
676 }
677
678 /* Reuse the page if possible. For notification packets and
679 * SKBs that fail to Rx correctly, add them back into the
680 * rx_free list for reuse later. */
681 spin_lock_irqsave(&rxq->lock, flags);
682 if (rxb->page != NULL) {
683 rxb->page_dma =
684 dma_map_page(trans->dev, rxb->page, 0,
685 PAGE_SIZE << trans_pcie->rx_page_order,
686 DMA_FROM_DEVICE);
687 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
688 /*
689 * free the page(s) as well to not break
690 * the invariant that the items on the used
691 * list have no page(s)
692 */
693 __free_pages(rxb->page, trans_pcie->rx_page_order);
694 rxb->page = NULL;
695 list_add_tail(&rxb->list, &rxq->rx_used);
696 } else {
697 list_add_tail(&rxb->list, &rxq->rx_free);
698 rxq->free_count++;
699 }
700 } else
701 list_add_tail(&rxb->list, &rxq->rx_used);
702 spin_unlock_irqrestore(&rxq->lock, flags);
703 }
704
705 /*
706 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
707 */
iwl_pcie_rx_handle(struct iwl_trans * trans)708 static void iwl_pcie_rx_handle(struct iwl_trans *trans)
709 {
710 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
711 struct iwl_rxq *rxq = &trans_pcie->rxq;
712 u32 r, i;
713 u8 fill_rx = 0;
714 u32 count = 8;
715 int total_empty;
716
717 /* uCode's read index (stored in shared DRAM) indicates the last Rx
718 * buffer that the driver may process (last buffer filled by ucode). */
719 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
720 i = rxq->read;
721
722 /* Rx interrupt, but nothing sent from uCode */
723 if (i == r)
724 IWL_DEBUG_RX(trans, "HW = SW = %d\n", r);
725
726 /* calculate total frames need to be restock after handling RX */
727 total_empty = r - rxq->write_actual;
728 if (total_empty < 0)
729 total_empty += RX_QUEUE_SIZE;
730
731 if (total_empty > (RX_QUEUE_SIZE / 2))
732 fill_rx = 1;
733
734 while (i != r) {
735 struct iwl_rx_mem_buffer *rxb;
736
737 rxb = rxq->queue[i];
738 rxq->queue[i] = NULL;
739
740 IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n",
741 r, i, rxb);
742 iwl_pcie_rx_handle_rb(trans, rxb);
743
744 i = (i + 1) & RX_QUEUE_MASK;
745 /* If there are a lot of unused frames,
746 * restock the Rx queue so ucode wont assert. */
747 if (fill_rx) {
748 count++;
749 if (count >= 8) {
750 rxq->read = i;
751 iwl_pcie_rx_replenish_now(trans);
752 count = 0;
753 }
754 }
755 }
756
757 /* Backtrack one entry */
758 rxq->read = i;
759 if (fill_rx)
760 iwl_pcie_rx_replenish_now(trans);
761 else
762 iwl_pcie_rxq_restock(trans);
763 }
764
765 /*
766 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
767 */
iwl_pcie_irq_handle_error(struct iwl_trans * trans)768 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
769 {
770 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
771
772 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
773 if (trans->cfg->internal_wimax_coex &&
774 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
775 APMS_CLK_VAL_MRB_FUNC_MODE) ||
776 (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
777 APMG_PS_CTRL_VAL_RESET_REQ))) {
778 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
779 iwl_op_mode_wimax_active(trans->op_mode);
780 wake_up(&trans_pcie->wait_command_queue);
781 return;
782 }
783
784 iwl_pcie_dump_csr(trans);
785 iwl_pcie_dump_fh(trans, NULL);
786
787 set_bit(STATUS_FW_ERROR, &trans_pcie->status);
788 clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
789 wake_up(&trans_pcie->wait_command_queue);
790
791 local_bh_disable();
792 iwl_op_mode_nic_error(trans->op_mode);
793 local_bh_enable();
794 }
795
iwl_pcie_irq_handler(int irq,void * dev_id)796 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
797 {
798 struct iwl_trans *trans = dev_id;
799 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
800 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
801 u32 inta = 0;
802 u32 handled = 0;
803 unsigned long flags;
804 u32 i;
805 #ifdef CONFIG_IWLWIFI_DEBUG
806 u32 inta_mask;
807 #endif
808
809 lock_map_acquire(&trans->sync_cmd_lockdep_map);
810
811 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
812
813 /* Ack/clear/reset pending uCode interrupts.
814 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
815 */
816 /* There is a hardware bug in the interrupt mask function that some
817 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
818 * they are disabled in the CSR_INT_MASK register. Furthermore the
819 * ICT interrupt handling mechanism has another bug that might cause
820 * these unmasked interrupts fail to be detected. We workaround the
821 * hardware bugs here by ACKing all the possible interrupts so that
822 * interrupt coalescing can still be achieved.
823 */
824 iwl_write32(trans, CSR_INT,
825 trans_pcie->inta | ~trans_pcie->inta_mask);
826
827 inta = trans_pcie->inta;
828
829 #ifdef CONFIG_IWLWIFI_DEBUG
830 if (iwl_have_debug_level(IWL_DL_ISR)) {
831 /* just for debug */
832 inta_mask = iwl_read32(trans, CSR_INT_MASK);
833 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
834 inta, inta_mask);
835 }
836 #endif
837
838 /* saved interrupt in inta variable now we can reset trans_pcie->inta */
839 trans_pcie->inta = 0;
840
841 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
842
843 /* Now service all interrupt bits discovered above. */
844 if (inta & CSR_INT_BIT_HW_ERR) {
845 IWL_ERR(trans, "Hardware error detected. Restarting.\n");
846
847 /* Tell the device to stop sending interrupts */
848 iwl_disable_interrupts(trans);
849
850 isr_stats->hw++;
851 iwl_pcie_irq_handle_error(trans);
852
853 handled |= CSR_INT_BIT_HW_ERR;
854
855 goto out;
856 }
857
858 #ifdef CONFIG_IWLWIFI_DEBUG
859 if (iwl_have_debug_level(IWL_DL_ISR)) {
860 /* NIC fires this, but we don't use it, redundant with WAKEUP */
861 if (inta & CSR_INT_BIT_SCD) {
862 IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
863 "the frame/frames.\n");
864 isr_stats->sch++;
865 }
866
867 /* Alive notification via Rx interrupt will do the real work */
868 if (inta & CSR_INT_BIT_ALIVE) {
869 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
870 isr_stats->alive++;
871 }
872 }
873 #endif
874 /* Safely ignore these bits for debug checks below */
875 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
876
877 /* HW RF KILL switch toggled */
878 if (inta & CSR_INT_BIT_RF_KILL) {
879 bool hw_rfkill;
880
881 hw_rfkill = iwl_is_rfkill_set(trans);
882 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
883 hw_rfkill ? "disable radio" : "enable radio");
884
885 isr_stats->rfkill++;
886
887 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
888 if (hw_rfkill) {
889 set_bit(STATUS_RFKILL, &trans_pcie->status);
890 if (test_and_clear_bit(STATUS_HCMD_ACTIVE,
891 &trans_pcie->status))
892 IWL_DEBUG_RF_KILL(trans,
893 "Rfkill while SYNC HCMD in flight\n");
894 wake_up(&trans_pcie->wait_command_queue);
895 } else {
896 clear_bit(STATUS_RFKILL, &trans_pcie->status);
897 }
898
899 handled |= CSR_INT_BIT_RF_KILL;
900 }
901
902 /* Chip got too hot and stopped itself */
903 if (inta & CSR_INT_BIT_CT_KILL) {
904 IWL_ERR(trans, "Microcode CT kill error detected.\n");
905 isr_stats->ctkill++;
906 handled |= CSR_INT_BIT_CT_KILL;
907 }
908
909 /* Error detected by uCode */
910 if (inta & CSR_INT_BIT_SW_ERR) {
911 IWL_ERR(trans, "Microcode SW error detected. "
912 " Restarting 0x%X.\n", inta);
913 isr_stats->sw++;
914 iwl_pcie_irq_handle_error(trans);
915 handled |= CSR_INT_BIT_SW_ERR;
916 }
917
918 /* uCode wakes up after power-down sleep */
919 if (inta & CSR_INT_BIT_WAKEUP) {
920 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
921 iwl_pcie_rxq_inc_wr_ptr(trans, &trans_pcie->rxq);
922 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++)
923 iwl_pcie_txq_inc_wr_ptr(trans, &trans_pcie->txq[i]);
924
925 isr_stats->wakeup++;
926
927 handled |= CSR_INT_BIT_WAKEUP;
928 }
929
930 /* All uCode command responses, including Tx command responses,
931 * Rx "responses" (frame-received notification), and other
932 * notifications from uCode come through here*/
933 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
934 CSR_INT_BIT_RX_PERIODIC)) {
935 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
936 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
937 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
938 iwl_write32(trans, CSR_FH_INT_STATUS,
939 CSR_FH_INT_RX_MASK);
940 }
941 if (inta & CSR_INT_BIT_RX_PERIODIC) {
942 handled |= CSR_INT_BIT_RX_PERIODIC;
943 iwl_write32(trans,
944 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
945 }
946 /* Sending RX interrupt require many steps to be done in the
947 * the device:
948 * 1- write interrupt to current index in ICT table.
949 * 2- dma RX frame.
950 * 3- update RX shared data to indicate last write index.
951 * 4- send interrupt.
952 * This could lead to RX race, driver could receive RX interrupt
953 * but the shared data changes does not reflect this;
954 * periodic interrupt will detect any dangling Rx activity.
955 */
956
957 /* Disable periodic interrupt; we use it as just a one-shot. */
958 iwl_write8(trans, CSR_INT_PERIODIC_REG,
959 CSR_INT_PERIODIC_DIS);
960
961 iwl_pcie_rx_handle(trans);
962
963 /*
964 * Enable periodic interrupt in 8 msec only if we received
965 * real RX interrupt (instead of just periodic int), to catch
966 * any dangling Rx interrupt. If it was just the periodic
967 * interrupt, there was no dangling Rx activity, and no need
968 * to extend the periodic interrupt; one-shot is enough.
969 */
970 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
971 iwl_write8(trans, CSR_INT_PERIODIC_REG,
972 CSR_INT_PERIODIC_ENA);
973
974 isr_stats->rx++;
975 }
976
977 /* This "Tx" DMA channel is used only for loading uCode */
978 if (inta & CSR_INT_BIT_FH_TX) {
979 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
980 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
981 isr_stats->tx++;
982 handled |= CSR_INT_BIT_FH_TX;
983 /* Wake up uCode load routine, now that load is complete */
984 trans_pcie->ucode_write_complete = true;
985 wake_up(&trans_pcie->ucode_write_waitq);
986 }
987
988 if (inta & ~handled) {
989 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
990 isr_stats->unhandled++;
991 }
992
993 if (inta & ~(trans_pcie->inta_mask)) {
994 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
995 inta & ~trans_pcie->inta_mask);
996 }
997
998 /* Re-enable all interrupts */
999 /* only Re-enable if disabled by irq */
1000 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status))
1001 iwl_enable_interrupts(trans);
1002 /* Re-enable RF_KILL if it occurred */
1003 else if (handled & CSR_INT_BIT_RF_KILL)
1004 iwl_enable_rfkill_int(trans);
1005
1006 out:
1007 lock_map_release(&trans->sync_cmd_lockdep_map);
1008 return IRQ_HANDLED;
1009 }
1010
1011 /******************************************************************************
1012 *
1013 * ICT functions
1014 *
1015 ******************************************************************************/
1016
1017 /* a device (PCI-E) page is 4096 bytes long */
1018 #define ICT_SHIFT 12
1019 #define ICT_SIZE (1 << ICT_SHIFT)
1020 #define ICT_COUNT (ICT_SIZE / sizeof(u32))
1021
1022 /* Free dram table */
iwl_pcie_free_ict(struct iwl_trans * trans)1023 void iwl_pcie_free_ict(struct iwl_trans *trans)
1024 {
1025 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1026
1027 if (trans_pcie->ict_tbl) {
1028 dma_free_coherent(trans->dev, ICT_SIZE,
1029 trans_pcie->ict_tbl,
1030 trans_pcie->ict_tbl_dma);
1031 trans_pcie->ict_tbl = NULL;
1032 trans_pcie->ict_tbl_dma = 0;
1033 }
1034 }
1035
1036 /*
1037 * allocate dram shared table, it is an aligned memory
1038 * block of ICT_SIZE.
1039 * also reset all data related to ICT table interrupt.
1040 */
iwl_pcie_alloc_ict(struct iwl_trans * trans)1041 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
1042 {
1043 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1044
1045 trans_pcie->ict_tbl =
1046 dma_alloc_coherent(trans->dev, ICT_SIZE,
1047 &trans_pcie->ict_tbl_dma,
1048 GFP_KERNEL);
1049 if (!trans_pcie->ict_tbl)
1050 return -ENOMEM;
1051
1052 /* just an API sanity check ... it is guaranteed to be aligned */
1053 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1054 iwl_pcie_free_ict(trans);
1055 return -EINVAL;
1056 }
1057
1058 IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
1059 (unsigned long long)trans_pcie->ict_tbl_dma);
1060
1061 IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
1062
1063 /* reset table and index to all 0 */
1064 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1065 trans_pcie->ict_index = 0;
1066
1067 /* add periodic RX interrupt */
1068 trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1069 return 0;
1070 }
1071
1072 /* Device is going up inform it about using ICT interrupt table,
1073 * also we need to tell the driver to start using ICT interrupt.
1074 */
iwl_pcie_reset_ict(struct iwl_trans * trans)1075 void iwl_pcie_reset_ict(struct iwl_trans *trans)
1076 {
1077 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1078 u32 val;
1079 unsigned long flags;
1080
1081 if (!trans_pcie->ict_tbl)
1082 return;
1083
1084 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1085 iwl_disable_interrupts(trans);
1086
1087 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1088
1089 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1090
1091 val |= CSR_DRAM_INT_TBL_ENABLE;
1092 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1093
1094 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1095
1096 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1097 trans_pcie->use_ict = true;
1098 trans_pcie->ict_index = 0;
1099 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1100 iwl_enable_interrupts(trans);
1101 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1102 }
1103
1104 /* Device is going down disable ict interrupt usage */
iwl_pcie_disable_ict(struct iwl_trans * trans)1105 void iwl_pcie_disable_ict(struct iwl_trans *trans)
1106 {
1107 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1108 unsigned long flags;
1109
1110 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1111 trans_pcie->use_ict = false;
1112 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1113 }
1114
1115 /* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */
iwl_pcie_isr(int irq,void * data)1116 static irqreturn_t iwl_pcie_isr(int irq, void *data)
1117 {
1118 struct iwl_trans *trans = data;
1119 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1120 u32 inta, inta_mask;
1121 #ifdef CONFIG_IWLWIFI_DEBUG
1122 u32 inta_fh;
1123 #endif
1124
1125 lockdep_assert_held(&trans_pcie->irq_lock);
1126
1127 trace_iwlwifi_dev_irq(trans->dev);
1128
1129 /* Disable (but don't clear!) interrupts here to avoid
1130 * back-to-back ISRs and sporadic interrupts from our NIC.
1131 * If we have something to service, the irq thread will re-enable ints.
1132 * If we *don't* have something, we'll re-enable before leaving here. */
1133 inta_mask = iwl_read32(trans, CSR_INT_MASK);
1134 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1135
1136 /* Discover which interrupts are active/pending */
1137 inta = iwl_read32(trans, CSR_INT);
1138
1139 if (inta & (~inta_mask)) {
1140 IWL_DEBUG_ISR(trans,
1141 "We got a masked interrupt (0x%08x)...Ack and ignore\n",
1142 inta & (~inta_mask));
1143 iwl_write32(trans, CSR_INT, inta & (~inta_mask));
1144 inta &= inta_mask;
1145 }
1146
1147 /* Ignore interrupt if there's nothing in NIC to service.
1148 * This may be due to IRQ shared with another device,
1149 * or due to sporadic interrupts thrown from our NIC. */
1150 if (!inta) {
1151 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1152 goto none;
1153 }
1154
1155 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1156 /* Hardware disappeared. It might have already raised
1157 * an interrupt */
1158 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1159 return IRQ_HANDLED;
1160 }
1161
1162 #ifdef CONFIG_IWLWIFI_DEBUG
1163 if (iwl_have_debug_level(IWL_DL_ISR)) {
1164 inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS);
1165 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1166 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1167 }
1168 #endif
1169
1170 trans_pcie->inta |= inta;
1171 /* the thread will service interrupts and re-enable them */
1172 if (likely(inta))
1173 return IRQ_WAKE_THREAD;
1174 else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1175 !trans_pcie->inta)
1176 iwl_enable_interrupts(trans);
1177 return IRQ_HANDLED;
1178
1179 none:
1180 /* re-enable interrupts here since we don't have anything to service. */
1181 /* only Re-enable if disabled by irq and no schedules tasklet. */
1182 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1183 !trans_pcie->inta)
1184 iwl_enable_interrupts(trans);
1185
1186 return IRQ_NONE;
1187 }
1188
1189 /* interrupt handler using ict table, with this interrupt driver will
1190 * stop using INTA register to get device's interrupt, reading this register
1191 * is expensive, device will write interrupts in ICT dram table, increment
1192 * index then will fire interrupt to driver, driver will OR all ICT table
1193 * entries from current index up to table entry with 0 value. the result is
1194 * the interrupt we need to service, driver will set the entries back to 0 and
1195 * set index.
1196 */
iwl_pcie_isr_ict(int irq,void * data)1197 irqreturn_t iwl_pcie_isr_ict(int irq, void *data)
1198 {
1199 struct iwl_trans *trans = data;
1200 struct iwl_trans_pcie *trans_pcie;
1201 u32 inta, inta_mask;
1202 u32 val = 0;
1203 u32 read;
1204 unsigned long flags;
1205
1206 if (!trans)
1207 return IRQ_NONE;
1208
1209 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1210
1211 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1212
1213 /* dram interrupt table not set yet,
1214 * use legacy interrupt.
1215 */
1216 if (unlikely(!trans_pcie->use_ict)) {
1217 irqreturn_t ret = iwl_pcie_isr(irq, data);
1218 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1219 return ret;
1220 }
1221
1222 trace_iwlwifi_dev_irq(trans->dev);
1223
1224 /* Disable (but don't clear!) interrupts here to avoid
1225 * back-to-back ISRs and sporadic interrupts from our NIC.
1226 * If we have something to service, the tasklet will re-enable ints.
1227 * If we *don't* have something, we'll re-enable before leaving here.
1228 */
1229 inta_mask = iwl_read32(trans, CSR_INT_MASK);
1230 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1231
1232 /* Ignore interrupt if there's nothing in NIC to service.
1233 * This may be due to IRQ shared with another device,
1234 * or due to sporadic interrupts thrown from our NIC. */
1235 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1236 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1237 if (!read) {
1238 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1239 goto none;
1240 }
1241
1242 /*
1243 * Collect all entries up to the first 0, starting from ict_index;
1244 * note we already read at ict_index.
1245 */
1246 do {
1247 val |= read;
1248 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1249 trans_pcie->ict_index, read);
1250 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1251 trans_pcie->ict_index =
1252 iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1253
1254 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1255 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1256 read);
1257 } while (read);
1258
1259 /* We should not get this value, just ignore it. */
1260 if (val == 0xffffffff)
1261 val = 0;
1262
1263 /*
1264 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1265 * (bit 15 before shifting it to 31) to clear when using interrupt
1266 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1267 * so we use them to decide on the real state of the Rx bit.
1268 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1269 */
1270 if (val & 0xC0000)
1271 val |= 0x8000;
1272
1273 inta = (0xff & val) | ((0xff00 & val) << 16);
1274 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1275 inta, inta_mask, val);
1276
1277 inta &= trans_pcie->inta_mask;
1278 trans_pcie->inta |= inta;
1279
1280 /* iwl_pcie_tasklet() will service interrupts and re-enable them */
1281 if (likely(inta)) {
1282 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1283 return IRQ_WAKE_THREAD;
1284 } else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1285 !trans_pcie->inta) {
1286 /* Allow interrupt if was disabled by this handler and
1287 * no tasklet was schedules, We should not enable interrupt,
1288 * tasklet will enable it.
1289 */
1290 iwl_enable_interrupts(trans);
1291 }
1292
1293 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1294 return IRQ_HANDLED;
1295
1296 none:
1297 /* re-enable interrupts here since we don't have anything to service.
1298 * only Re-enable if disabled by irq.
1299 */
1300 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1301 !trans_pcie->inta)
1302 iwl_enable_interrupts(trans);
1303
1304 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1305 return IRQ_NONE;
1306 }
1307