1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_MR_H 8 #define __QLA_MR_H 9 10 /* 11 * The PCI VendorID and DeviceID for our board. 12 */ 13 #define PCI_DEVICE_ID_QLOGIC_ISPF001 0xF001 14 15 /* FX00 specific definitions */ 16 17 #define FX00_COMMAND_TYPE_7 0x07 /* Command Type 7 entry for 7XXX */ 18 struct cmd_type_7_fx00 { 19 uint8_t entry_type; /* Entry type. */ 20 uint8_t entry_count; /* Entry count. */ 21 uint8_t sys_define; /* System defined. */ 22 uint8_t entry_status; /* Entry Status. */ 23 24 uint32_t handle; /* System handle. */ 25 uint32_t handle_hi; 26 27 uint16_t tgt_idx; /* Target Idx. */ 28 uint16_t timeout; /* Command timeout. */ 29 30 uint16_t dseg_count; /* Data segment count. */ 31 uint16_t scsi_rsp_dsd_len; 32 33 struct scsi_lun lun; /* LUN (LE). */ 34 35 uint8_t cntrl_flags; 36 37 uint8_t task_mgmt_flags; /* Task management flags. */ 38 39 uint8_t task; 40 41 uint8_t crn; 42 43 uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */ 44 uint32_t byte_count; /* Total byte count. */ 45 46 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 47 uint32_t dseg_0_len; /* Data segment 0 length. */ 48 }; 49 50 /* 51 * ISP queue - marker entry structure definition. 52 */ 53 struct mrk_entry_fx00 { 54 uint8_t entry_type; /* Entry type. */ 55 uint8_t entry_count; /* Entry count. */ 56 uint8_t handle_count; /* Handle count. */ 57 uint8_t entry_status; /* Entry Status. */ 58 59 uint32_t handle; /* System handle. */ 60 uint32_t handle_hi; /* System handle. */ 61 62 uint16_t tgt_id; /* Target ID. */ 63 64 uint8_t modifier; /* Modifier (7-0). */ 65 uint8_t reserved_1; 66 67 uint8_t reserved_2[5]; 68 69 uint8_t lun[8]; /* FCP LUN (BE). */ 70 uint8_t reserved_3[36]; 71 }; 72 73 74 #define STATUS_TYPE_FX00 0x01 /* Status entry. */ 75 struct sts_entry_fx00 { 76 uint8_t entry_type; /* Entry type. */ 77 uint8_t entry_count; /* Entry count. */ 78 uint8_t sys_define; /* System defined. */ 79 uint8_t entry_status; /* Entry Status. */ 80 81 uint32_t handle; /* System handle. */ 82 uint32_t handle_hi; /* System handle. */ 83 84 uint16_t comp_status; /* Completion status. */ 85 uint16_t reserved_0; /* OX_ID used by the firmware. */ 86 87 uint32_t residual_len; /* FW calc residual transfer length. */ 88 89 uint16_t reserved_1; 90 uint16_t state_flags; /* State flags. */ 91 92 uint16_t reserved_2; 93 uint16_t scsi_status; /* SCSI status. */ 94 95 uint32_t sense_len; /* FCP SENSE length. */ 96 uint8_t data[32]; /* FCP response/sense information. */ 97 }; 98 99 100 #define MAX_HANDLE_COUNT 15 101 #define MULTI_STATUS_TYPE_FX00 0x0D 102 103 struct multi_sts_entry_fx00 { 104 uint8_t entry_type; /* Entry type. */ 105 uint8_t sys_define; /* System defined. */ 106 uint8_t handle_count; 107 uint8_t entry_status; 108 109 uint32_t handles[MAX_HANDLE_COUNT]; 110 }; 111 112 #define TSK_MGMT_IOCB_TYPE_FX00 0x05 113 struct tsk_mgmt_entry_fx00 { 114 uint8_t entry_type; /* Entry type. */ 115 uint8_t entry_count; /* Entry count. */ 116 uint8_t sys_define; 117 uint8_t entry_status; /* Entry Status. */ 118 119 uint32_t handle; /* System handle. */ 120 121 uint32_t handle_hi; /* System handle. */ 122 123 uint16_t tgt_id; /* Target Idx. */ 124 125 uint16_t reserved_1; 126 127 uint16_t delay; /* Activity delay in seconds. */ 128 129 uint16_t timeout; /* Command timeout. */ 130 131 struct scsi_lun lun; /* LUN (LE). */ 132 133 uint32_t control_flags; /* Control Flags. */ 134 135 uint8_t reserved_2[32]; 136 }; 137 138 139 #define ABORT_IOCB_TYPE_FX00 0x08 /* Abort IOCB status. */ 140 struct abort_iocb_entry_fx00 { 141 uint8_t entry_type; /* Entry type. */ 142 uint8_t entry_count; /* Entry count. */ 143 uint8_t sys_define; /* System defined. */ 144 uint8_t entry_status; /* Entry Status. */ 145 146 uint32_t handle; /* System handle. */ 147 uint32_t handle_hi; /* System handle. */ 148 149 uint16_t tgt_id_sts; /* Completion status. */ 150 uint16_t options; 151 152 uint32_t abort_handle; /* System handle. */ 153 uint32_t abort_handle_hi; /* System handle. */ 154 155 uint16_t req_que_no; 156 uint8_t reserved_1[38]; 157 }; 158 159 #define IOCTL_IOSB_TYPE_FX00 0x0C 160 struct ioctl_iocb_entry_fx00 { 161 uint8_t entry_type; /* Entry type. */ 162 uint8_t entry_count; /* Entry count. */ 163 uint8_t sys_define; /* System defined. */ 164 uint8_t entry_status; /* Entry Status. */ 165 166 uint32_t handle; /* System handle. */ 167 uint32_t reserved_0; /* System handle. */ 168 169 uint16_t comp_func_num; 170 uint16_t fw_iotcl_flags; 171 172 uint32_t dataword_r; /* Data word returned */ 173 uint32_t adapid; /* Adapter ID */ 174 uint32_t adapid_hi; /* Adapter ID high */ 175 uint32_t reserved_1; 176 177 uint32_t seq_no; 178 uint8_t reserved_2[20]; 179 uint32_t residuallen; 180 uint32_t status; 181 }; 182 183 #define STATUS_CONT_TYPE_FX00 0x04 184 185 #define FX00_IOCB_TYPE 0x0B 186 struct fxdisc_entry_fx00 { 187 uint8_t entry_type; /* Entry type. */ 188 uint8_t entry_count; /* Entry count. */ 189 uint8_t sys_define; /* System Defined. */ 190 uint8_t entry_status; /* Entry Status. */ 191 192 uint32_t handle; /* System handle. */ 193 uint32_t reserved_0; /* System handle. */ 194 195 uint16_t func_num; 196 uint16_t req_xfrcnt; 197 uint16_t req_dsdcnt; 198 uint16_t rsp_xfrcnt; 199 uint16_t rsp_dsdcnt; 200 uint8_t flags; 201 uint8_t reserved_1; 202 203 uint32_t dseg_rq_address[2]; /* Data segment 0 address. */ 204 uint32_t dseg_rq_len; /* Data segment 0 length. */ 205 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ 206 uint32_t dseg_rsp_len; /* Data segment 1 length. */ 207 208 uint32_t dataword; 209 uint32_t adapid; 210 uint32_t adapid_hi; 211 uint32_t dataword_extra; 212 }; 213 214 struct qlafx00_tgt_node_info { 215 uint8_t tgt_node_wwpn[WWN_SIZE]; 216 uint8_t tgt_node_wwnn[WWN_SIZE]; 217 uint32_t tgt_node_state; 218 uint8_t reserved[128]; 219 uint32_t reserved_1[8]; 220 uint64_t reserved_2[4]; 221 } __packed; 222 223 #define QLAFX00_TGT_NODE_INFO sizeof(struct qlafx00_tgt_node_info) 224 225 #define QLAFX00_LINK_STATUS_DOWN 0x10 226 #define QLAFX00_LINK_STATUS_UP 0x11 227 228 #define QLAFX00_PORT_SPEED_2G 0x2 229 #define QLAFX00_PORT_SPEED_4G 0x4 230 #define QLAFX00_PORT_SPEED_8G 0x8 231 #define QLAFX00_PORT_SPEED_10G 0xa 232 struct port_info_data { 233 uint8_t port_state; 234 uint8_t port_type; 235 uint16_t port_identifier; 236 uint32_t up_port_state; 237 uint8_t fw_ver_num[32]; 238 uint8_t portal_attrib; 239 uint16_t host_option; 240 uint8_t reset_delay; 241 uint8_t pdwn_retry_cnt; 242 uint16_t max_luns2tgt; 243 uint8_t risc_ver; 244 uint8_t pconn_option; 245 uint16_t risc_option; 246 uint16_t max_frame_len; 247 uint16_t max_iocb_alloc; 248 uint16_t exec_throttle; 249 uint8_t retry_cnt; 250 uint8_t retry_delay; 251 uint8_t port_name[8]; 252 uint8_t port_id[3]; 253 uint8_t link_status; 254 uint8_t plink_rate; 255 uint32_t link_config; 256 uint16_t adap_haddr; 257 uint8_t tgt_disc; 258 uint8_t log_tout; 259 uint8_t node_name[8]; 260 uint16_t erisc_opt1; 261 uint8_t resp_acc_tmr; 262 uint8_t intr_del_tmr; 263 uint8_t erisc_opt2; 264 uint8_t alt_port_name[8]; 265 uint8_t alt_node_name[8]; 266 uint8_t link_down_tout; 267 uint8_t conn_type; 268 uint8_t fc_fw_mode; 269 uint32_t uiReserved[48]; 270 } __packed; 271 272 /* OS Type Designations */ 273 #define OS_TYPE_UNKNOWN 0 274 #define OS_TYPE_LINUX 2 275 276 /* Linux Info */ 277 #define SYSNAME_LENGTH 128 278 #define NODENAME_LENGTH 64 279 #define RELEASE_LENGTH 64 280 #define VERSION_LENGTH 64 281 #define MACHINE_LENGTH 64 282 #define DOMNAME_LENGTH 64 283 284 struct host_system_info { 285 uint32_t os_type; 286 char sysname[SYSNAME_LENGTH]; 287 char nodename[NODENAME_LENGTH]; 288 char release[RELEASE_LENGTH]; 289 char version[VERSION_LENGTH]; 290 char machine[MACHINE_LENGTH]; 291 char domainname[DOMNAME_LENGTH]; 292 char hostdriver[VERSION_LENGTH]; 293 uint32_t reserved[64]; 294 } __packed; 295 296 struct register_host_info { 297 struct host_system_info hsi; /* host system info */ 298 uint64_t utc; /* UTC (system time) */ 299 uint32_t reserved[64]; /* future additions */ 300 } __packed; 301 302 303 #define QLAFX00_PORT_DATA_INFO (sizeof(struct port_info_data)) 304 #define QLAFX00_TGT_NODE_LIST_SIZE (sizeof(uint32_t) * 32) 305 306 struct config_info_data { 307 uint8_t product_name[256]; 308 uint8_t symbolic_name[64]; 309 uint8_t serial_num[32]; 310 uint8_t hw_version[16]; 311 uint8_t fw_version[16]; 312 uint8_t uboot_version[16]; 313 uint8_t fru_serial_num[32]; 314 315 uint8_t fc_port_count; 316 uint8_t iscsi_port_count; 317 uint8_t reserved1[2]; 318 319 uint8_t mode; 320 uint8_t log_level; 321 uint8_t reserved2[2]; 322 323 uint32_t log_size; 324 325 uint8_t tgt_pres_mode; 326 uint8_t iqn_flags; 327 uint8_t lun_mapping; 328 329 uint64_t adapter_id; 330 331 uint32_t cluster_key_len; 332 uint8_t cluster_key[10]; 333 334 uint64_t cluster_master_id; 335 uint64_t cluster_slave_id; 336 uint8_t cluster_flags; 337 } __packed; 338 339 #define FXDISC_GET_CONFIG_INFO 0x01 340 #define FXDISC_GET_PORT_INFO 0x02 341 #define FXDISC_GET_TGT_NODE_INFO 0x80 342 #define FXDISC_GET_TGT_NODE_LIST 0x81 343 #define FXDISC_REG_HOST_INFO 0x99 344 345 #define QLAFX00_HBA_ICNTRL_REG 0x21B08 346 #define QLAFX00_ICR_ENB_MASK 0x80000000 347 #define QLAFX00_ICR_DIS_MASK 0x7fffffff 348 #define QLAFX00_HST_RST_REG 0x18264 349 #define QLAFX00_HST_TO_HBA_REG 0x20A04 350 #define QLAFX00_HBA_TO_HOST_REG 0x21B70 351 #define QLAFX00_HST_INT_STS_BITS 0x7 352 #define QLAFX00_BAR1_BASE_ADDR_REG 0x40018 353 #define QLAFX00_PEX0_WIN0_BASE_ADDR_REG 0x41824 354 355 #define QLAFX00_INTR_MB_CMPLT 0x1 356 #define QLAFX00_INTR_RSP_CMPLT 0x2 357 #define QLAFX00_INTR_MB_RSP_CMPLT 0x3 358 #define QLAFX00_INTR_ASYNC_CMPLT 0x4 359 #define QLAFX00_INTR_MB_ASYNC_CMPLT 0x5 360 #define QLAFX00_INTR_RSP_ASYNC_CMPLT 0x6 361 #define QLAFX00_INTR_ALL_CMPLT 0x7 362 363 #define QLAFX00_MBA_SYSTEM_ERR 0x8002 364 #define QLAFX00_MBA_LINK_UP 0x8011 365 #define QLAFX00_MBA_LINK_DOWN 0x8012 366 #define QLAFX00_MBA_PORT_UPDATE 0x8014 367 #define QLAFX00_MBA_SHUTDOWN_RQSTD 0x8062 368 369 #define SOC_SW_RST_CONTROL_REG_CORE0 0x0020800 370 #define SOC_FABRIC_RST_CONTROL_REG 0x0020840 371 #define SOC_FABRIC_CONTROL_REG 0x0020200 372 #define SOC_FABRIC_CONFIG_REG 0x0020204 373 374 #define SOC_INTERRUPT_SOURCE_I_CONTROL_REG 0x0020B00 375 #define SOC_CORE_TIMER_REG 0x0021850 376 #define SOC_IRQ_ACK_REG 0x00218b4 377 378 #define CONTINUE_A64_TYPE_FX00 0x03 /* Continuation entry. */ 379 380 #define QLAFX00_SET_HST_INTR(ha, value) \ 381 WRT_REG_DWORD((ha)->cregbase + QLAFX00_HST_TO_HBA_REG, \ 382 value) 383 384 #define QLAFX00_CLR_HST_INTR(ha, value) \ 385 WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \ 386 ~value) 387 388 #define QLAFX00_RD_INTR_REG(ha) \ 389 RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG) 390 391 #define QLAFX00_CLR_INTR_REG(ha, value) \ 392 WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \ 393 ~value) 394 395 #define QLAFX00_SET_HBA_SOC_REG(ha, off, val)\ 396 WRT_REG_DWORD((ha)->cregbase + off, val) 397 398 #define QLAFX00_GET_HBA_SOC_REG(ha, off)\ 399 RD_REG_DWORD((ha)->cregbase + off) 400 401 #define QLAFX00_HBA_RST_REG(ha, val)\ 402 WRT_REG_DWORD((ha)->cregbase + QLAFX00_HST_RST_REG, val) 403 404 #define QLAFX00_RD_ICNTRL_REG(ha) \ 405 RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG) 406 407 #define QLAFX00_ENABLE_ICNTRL_REG(ha) \ 408 WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \ 409 (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) | \ 410 QLAFX00_ICR_ENB_MASK)) 411 412 #define QLAFX00_DISABLE_ICNTRL_REG(ha) \ 413 WRT_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \ 414 (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) & \ 415 QLAFX00_ICR_DIS_MASK)) 416 417 #define QLAFX00_RD_REG(ha, off) \ 418 RD_REG_DWORD((ha)->cregbase + off) 419 420 #define QLAFX00_WR_REG(ha, off, val) \ 421 WRT_REG_DWORD((ha)->cregbase + off, val) 422 423 struct qla_mt_iocb_rqst_fx00 { 424 uint32_t reserved_0; 425 426 uint16_t func_type; 427 uint8_t flags; 428 uint8_t reserved_1; 429 430 uint32_t dataword; 431 432 uint32_t adapid; 433 uint32_t adapid_hi; 434 435 uint32_t dataword_extra; 436 437 uint32_t req_len; 438 439 uint32_t rsp_len; 440 }; 441 442 struct qla_mt_iocb_rsp_fx00 { 443 uint32_t reserved_1; 444 445 uint16_t func_type; 446 uint16_t ioctl_flags; 447 448 uint32_t ioctl_data; 449 450 uint32_t adapid; 451 uint32_t adapid_hi; 452 453 uint32_t reserved_2; 454 uint32_t seq_number; 455 456 uint8_t reserved_3[20]; 457 458 int32_t res_count; 459 460 uint32_t status; 461 }; 462 463 464 #define MAILBOX_REGISTER_COUNT_FX00 16 465 #define AEN_MAILBOX_REGISTER_COUNT_FX00 8 466 #define MAX_FIBRE_DEVICES_FX00 512 467 #define MAX_LUNS_FX00 0x1024 468 #define MAX_TARGETS_FX00 MAX_ISA_DEVICES 469 #define REQUEST_ENTRY_CNT_FX00 512 /* Number of request entries. */ 470 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 471 472 /* 473 * Firmware state codes for QLAFX00 adapters 474 */ 475 #define FSTATE_FX00_CONFIG_WAIT 0x0000 /* Waiting for driver to issue 476 * Initialize FW Mbox cmd 477 */ 478 #define FSTATE_FX00_INITIALIZED 0x1000 /* FW has been initialized by 479 * the driver 480 */ 481 482 #define FX00_DEF_RATOV 10 483 484 struct mr_data_fx00 { 485 uint8_t product_name[256]; 486 uint8_t symbolic_name[64]; 487 uint8_t serial_num[32]; 488 uint8_t hw_version[16]; 489 uint8_t fw_version[16]; 490 uint8_t uboot_version[16]; 491 uint8_t fru_serial_num[32]; 492 fc_port_t fcport; /* fcport used for requests 493 * that are not linked 494 * to a particular target 495 */ 496 uint8_t fw_hbt_en; 497 uint8_t fw_hbt_cnt; 498 uint8_t fw_hbt_miss_cnt; 499 uint32_t old_fw_hbt_cnt; 500 uint16_t fw_reset_timer_tick; 501 uint8_t fw_reset_timer_exp; 502 uint32_t old_aenmbx0_state; 503 }; 504 505 #define QLAFX00_LOOP_DOWN_TIME 615 /* 600 */ 506 #define QLAFX00_HEARTBEAT_INTERVAL 6 /* number of seconds */ 507 #define QLAFX00_HEARTBEAT_MISS_CNT 3 /* number of miss */ 508 #define QLAFX00_RESET_INTERVAL 120 /* number of seconds */ 509 #define QLAFX00_MAX_RESET_INTERVAL 600 /* number of seconds */ 510 #endif 511