1 /*
2 * Low-Level PCI Access for i386 machines.
3 *
4 * (c) 1999 Martin Mares <mj@ucw.cz>
5 */
6
7 #undef DEBUG
8
9 #ifdef DEBUG
10 #define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__)
11 #else
12 #define DBG(fmt, ...) \
13 do { \
14 if (0) \
15 printk(fmt, ##__VA_ARGS__); \
16 } while (0)
17 #endif
18
19 #define PCI_PROBE_BIOS 0x0001
20 #define PCI_PROBE_CONF1 0x0002
21 #define PCI_PROBE_CONF2 0x0004
22 #define PCI_PROBE_MMCONF 0x0008
23 #define PCI_PROBE_MASK 0x000f
24 #define PCI_PROBE_NOEARLY 0x0010
25
26 #define PCI_NO_CHECKS 0x0400
27 #define PCI_USE_PIRQ_MASK 0x0800
28 #define PCI_ASSIGN_ROMS 0x1000
29 #define PCI_BIOS_IRQ_SCAN 0x2000
30 #define PCI_ASSIGN_ALL_BUSSES 0x4000
31 #define PCI_CAN_SKIP_ISA_ALIGN 0x8000
32 #define PCI_USE__CRS 0x10000
33 #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
34 #define PCI_HAS_IO_ECS 0x40000
35 #define PCI_NOASSIGN_ROMS 0x80000
36 #define PCI_ROOT_NO_CRS 0x100000
37 #define PCI_NOASSIGN_BARS 0x200000
38
39 extern unsigned int pci_probe;
40 extern unsigned long pirq_table_addr;
41
42 enum pci_bf_sort_state {
43 pci_bf_sort_default,
44 pci_force_nobf,
45 pci_force_bf,
46 pci_dmi_bf,
47 };
48
49 /* pci-i386.c */
50
51 void pcibios_resource_survey(void);
52 void pcibios_set_cache_line_size(void);
53
54 /* pci-pc.c */
55
56 extern int pcibios_last_bus;
57 extern struct pci_ops pci_root_ops;
58
59 void pcibios_scan_specific_bus(int busn);
60
61 /* pci-irq.c */
62
63 struct irq_info {
64 u8 bus, devfn; /* Bus, device and function */
65 struct {
66 u8 link; /* IRQ line ID, chipset dependent,
67 0 = not routed */
68 u16 bitmap; /* Available IRQs */
69 } __attribute__((packed)) irq[4];
70 u8 slot; /* Slot number, 0=onboard */
71 u8 rfu;
72 } __attribute__((packed));
73
74 struct irq_routing_table {
75 u32 signature; /* PIRQ_SIGNATURE should be here */
76 u16 version; /* PIRQ_VERSION */
77 u16 size; /* Table size in bytes */
78 u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
79 u16 exclusive_irqs; /* IRQs devoted exclusively to
80 PCI usage */
81 u16 rtr_vendor, rtr_device; /* Vendor and device ID of
82 interrupt router */
83 u32 miniport_data; /* Crap */
84 u8 rfu[11];
85 u8 checksum; /* Modulo 256 checksum must give 0 */
86 struct irq_info slots[0];
87 } __attribute__((packed));
88
89 extern unsigned int pcibios_irq_mask;
90
91 extern raw_spinlock_t pci_config_lock;
92
93 extern int (*pcibios_enable_irq)(struct pci_dev *dev);
94 extern void (*pcibios_disable_irq)(struct pci_dev *dev);
95
96 struct pci_raw_ops {
97 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
98 int reg, int len, u32 *val);
99 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
100 int reg, int len, u32 val);
101 };
102
103 extern const struct pci_raw_ops *raw_pci_ops;
104 extern const struct pci_raw_ops *raw_pci_ext_ops;
105
106 extern const struct pci_raw_ops pci_mmcfg;
107 extern const struct pci_raw_ops pci_direct_conf1;
108 extern bool port_cf9_safe;
109
110 /* arch_initcall level */
111 extern int pci_direct_probe(void);
112 extern void pci_direct_init(int type);
113 extern void pci_pcbios_init(void);
114 extern void __init dmi_check_pciprobe(void);
115 extern void __init dmi_check_skip_isa_align(void);
116
117 /* some common used subsys_initcalls */
118 extern int __init pci_acpi_init(void);
119 extern void __init pcibios_irq_init(void);
120 extern int __init pcibios_init(void);
121 extern int pci_legacy_init(void);
122 extern void pcibios_fixup_irqs(void);
123
124 /* pci-mmconfig.c */
125
126 /* "PCI MMCONFIG %04x [bus %02x-%02x]" */
127 #define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
128
129 struct pci_mmcfg_region {
130 struct list_head list;
131 struct resource res;
132 u64 address;
133 char __iomem *virt;
134 u16 segment;
135 u8 start_bus;
136 u8 end_bus;
137 char name[PCI_MMCFG_RESOURCE_NAME_LEN];
138 };
139
140 extern int __init pci_mmcfg_arch_init(void);
141 extern void __init pci_mmcfg_arch_free(void);
142 extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg);
143 extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg);
144 extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
145 phys_addr_t addr);
146 extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);
147 extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
148
149 extern struct list_head pci_mmcfg_list;
150
151 #define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
152
153 /*
154 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
155 * on their northbrige except through the * %eax register. As such, you MUST
156 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
157 * accessor functions.
158 * In fact just use pci_config_*, nothing else please.
159 */
mmio_config_readb(void __iomem * pos)160 static inline unsigned char mmio_config_readb(void __iomem *pos)
161 {
162 u8 val;
163 asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
164 return val;
165 }
166
mmio_config_readw(void __iomem * pos)167 static inline unsigned short mmio_config_readw(void __iomem *pos)
168 {
169 u16 val;
170 asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
171 return val;
172 }
173
mmio_config_readl(void __iomem * pos)174 static inline unsigned int mmio_config_readl(void __iomem *pos)
175 {
176 u32 val;
177 asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
178 return val;
179 }
180
mmio_config_writeb(void __iomem * pos,u8 val)181 static inline void mmio_config_writeb(void __iomem *pos, u8 val)
182 {
183 asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
184 }
185
mmio_config_writew(void __iomem * pos,u16 val)186 static inline void mmio_config_writew(void __iomem *pos, u16 val)
187 {
188 asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
189 }
190
mmio_config_writel(void __iomem * pos,u32 val)191 static inline void mmio_config_writel(void __iomem *pos, u32 val)
192 {
193 asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
194 }
195
196 #ifdef CONFIG_PCI
197 # ifdef CONFIG_ACPI
198 # define x86_default_pci_init pci_acpi_init
199 # else
200 # define x86_default_pci_init pci_legacy_init
201 # endif
202 # define x86_default_pci_init_irq pcibios_irq_init
203 # define x86_default_pci_fixup_irqs pcibios_fixup_irqs
204 #else
205 # define x86_default_pci_init NULL
206 # define x86_default_pci_init_irq NULL
207 # define x86_default_pci_fixup_irqs NULL
208 #endif
209