1 #include <core/client.h>
2 #include <core/os.h>
3 #include <core/class.h>
4 #include <core/engctx.h>
5 #include <core/handle.h>
6 #include <core/enum.h>
7
8 #include <subdev/timer.h>
9 #include <subdev/fb.h>
10
11 #include <engine/graph.h>
12 #include <engine/fifo.h>
13
14 #include "nv20.h"
15 #include "regs.h"
16
17 /*******************************************************************************
18 * Graphics object classes
19 ******************************************************************************/
20
21 static struct nouveau_oclass
22 nv20_graph_sclass[] = {
23 { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */
24 { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */
25 { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */
26 { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */
27 { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */
28 { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */
29 { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */
30 { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */
31 { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */
32 { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */
33 { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */
34 { 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */
35 { 0x0097, &nv04_graph_ofuncs, NULL }, /* kelvin */
36 { 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */
37 { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */
38 {},
39 };
40
41 /*******************************************************************************
42 * PGRAPH context
43 ******************************************************************************/
44
45 static int
nv20_graph_context_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)46 nv20_graph_context_ctor(struct nouveau_object *parent,
47 struct nouveau_object *engine,
48 struct nouveau_oclass *oclass, void *data, u32 size,
49 struct nouveau_object **pobject)
50 {
51 struct nv20_graph_chan *chan;
52 int ret, i;
53
54 ret = nouveau_graph_context_create(parent, engine, oclass, NULL,
55 0x37f0, 16, NVOBJ_FLAG_ZERO_ALLOC,
56 &chan);
57 *pobject = nv_object(chan);
58 if (ret)
59 return ret;
60
61 chan->chid = nouveau_fifo_chan(parent)->chid;
62
63 nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
64 nv_wo32(chan, 0x033c, 0xffff0000);
65 nv_wo32(chan, 0x03a0, 0x0fff0000);
66 nv_wo32(chan, 0x03a4, 0x0fff0000);
67 nv_wo32(chan, 0x047c, 0x00000101);
68 nv_wo32(chan, 0x0490, 0x00000111);
69 nv_wo32(chan, 0x04a8, 0x44400000);
70 for (i = 0x04d4; i <= 0x04e0; i += 4)
71 nv_wo32(chan, i, 0x00030303);
72 for (i = 0x04f4; i <= 0x0500; i += 4)
73 nv_wo32(chan, i, 0x00080000);
74 for (i = 0x050c; i <= 0x0518; i += 4)
75 nv_wo32(chan, i, 0x01012000);
76 for (i = 0x051c; i <= 0x0528; i += 4)
77 nv_wo32(chan, i, 0x000105b8);
78 for (i = 0x052c; i <= 0x0538; i += 4)
79 nv_wo32(chan, i, 0x00080008);
80 for (i = 0x055c; i <= 0x0598; i += 4)
81 nv_wo32(chan, i, 0x07ff0000);
82 nv_wo32(chan, 0x05a4, 0x4b7fffff);
83 nv_wo32(chan, 0x05fc, 0x00000001);
84 nv_wo32(chan, 0x0604, 0x00004000);
85 nv_wo32(chan, 0x0610, 0x00000001);
86 nv_wo32(chan, 0x0618, 0x00040000);
87 nv_wo32(chan, 0x061c, 0x00010000);
88 for (i = 0x1c1c; i <= 0x248c; i += 16) {
89 nv_wo32(chan, (i + 0), 0x10700ff9);
90 nv_wo32(chan, (i + 4), 0x0436086c);
91 nv_wo32(chan, (i + 8), 0x000c001b);
92 }
93 nv_wo32(chan, 0x281c, 0x3f800000);
94 nv_wo32(chan, 0x2830, 0x3f800000);
95 nv_wo32(chan, 0x285c, 0x40000000);
96 nv_wo32(chan, 0x2860, 0x3f800000);
97 nv_wo32(chan, 0x2864, 0x3f000000);
98 nv_wo32(chan, 0x286c, 0x40000000);
99 nv_wo32(chan, 0x2870, 0x3f800000);
100 nv_wo32(chan, 0x2878, 0xbf800000);
101 nv_wo32(chan, 0x2880, 0xbf800000);
102 nv_wo32(chan, 0x34a4, 0x000fe000);
103 nv_wo32(chan, 0x3530, 0x000003f8);
104 nv_wo32(chan, 0x3540, 0x002fe000);
105 for (i = 0x355c; i <= 0x3578; i += 4)
106 nv_wo32(chan, i, 0x001c527c);
107 return 0;
108 }
109
110 int
nv20_graph_context_init(struct nouveau_object * object)111 nv20_graph_context_init(struct nouveau_object *object)
112 {
113 struct nv20_graph_priv *priv = (void *)object->engine;
114 struct nv20_graph_chan *chan = (void *)object;
115 int ret;
116
117 ret = nouveau_graph_context_init(&chan->base);
118 if (ret)
119 return ret;
120
121 nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4);
122 return 0;
123 }
124
125 int
nv20_graph_context_fini(struct nouveau_object * object,bool suspend)126 nv20_graph_context_fini(struct nouveau_object *object, bool suspend)
127 {
128 struct nv20_graph_priv *priv = (void *)object->engine;
129 struct nv20_graph_chan *chan = (void *)object;
130 int chid = -1;
131
132 nv_mask(priv, 0x400720, 0x00000001, 0x00000000);
133 if (nv_rd32(priv, 0x400144) & 0x00010000)
134 chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24;
135 if (chan->chid == chid) {
136 nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4);
137 nv_wr32(priv, 0x400788, 0x00000002);
138 nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
139 nv_wr32(priv, 0x400144, 0x10000000);
140 nv_mask(priv, 0x400148, 0xff000000, 0x1f000000);
141 }
142 nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
143
144 nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000);
145 return nouveau_graph_context_fini(&chan->base, suspend);
146 }
147
148 static struct nouveau_oclass
149 nv20_graph_cclass = {
150 .handle = NV_ENGCTX(GR, 0x20),
151 .ofuncs = &(struct nouveau_ofuncs) {
152 .ctor = nv20_graph_context_ctor,
153 .dtor = _nouveau_graph_context_dtor,
154 .init = nv20_graph_context_init,
155 .fini = nv20_graph_context_fini,
156 .rd32 = _nouveau_graph_context_rd32,
157 .wr32 = _nouveau_graph_context_wr32,
158 },
159 };
160
161 /*******************************************************************************
162 * PGRAPH engine/subdev functions
163 ******************************************************************************/
164
165 void
nv20_graph_tile_prog(struct nouveau_engine * engine,int i)166 nv20_graph_tile_prog(struct nouveau_engine *engine, int i)
167 {
168 struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
169 struct nouveau_fifo *pfifo = nouveau_fifo(engine);
170 struct nv20_graph_priv *priv = (void *)engine;
171 unsigned long flags;
172
173 pfifo->pause(pfifo, &flags);
174 nv04_graph_idle(priv);
175
176 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit);
177 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch);
178 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr);
179
180 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
181 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit);
182 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
183 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch);
184 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
185 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr);
186
187 if (nv_device(engine)->chipset != 0x34) {
188 nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
189 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
190 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp);
191 }
192
193 pfifo->start(pfifo, &flags);
194 }
195
196 void
nv20_graph_intr(struct nouveau_subdev * subdev)197 nv20_graph_intr(struct nouveau_subdev *subdev)
198 {
199 struct nouveau_engine *engine = nv_engine(subdev);
200 struct nouveau_object *engctx;
201 struct nouveau_handle *handle;
202 struct nv20_graph_priv *priv = (void *)subdev;
203 u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
204 u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
205 u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
206 u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR);
207 u32 chid = (addr & 0x01f00000) >> 20;
208 u32 subc = (addr & 0x00070000) >> 16;
209 u32 mthd = (addr & 0x00001ffc);
210 u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA);
211 u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff;
212 u32 show = stat;
213
214 engctx = nouveau_engctx_get(engine, chid);
215 if (stat & NV_PGRAPH_INTR_ERROR) {
216 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
217 handle = nouveau_handle_get_class(engctx, class);
218 if (handle && !nv_call(handle->object, mthd, data))
219 show &= ~NV_PGRAPH_INTR_ERROR;
220 nouveau_handle_put(handle);
221 }
222 }
223
224 nv_wr32(priv, NV03_PGRAPH_INTR, stat);
225 nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001);
226
227 if (show) {
228 nv_error(priv, "%s", "");
229 nouveau_bitfield_print(nv10_graph_intr_name, show);
230 pr_cont(" nsource:");
231 nouveau_bitfield_print(nv04_graph_nsource, nsource);
232 pr_cont(" nstatus:");
233 nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
234 pr_cont("\n");
235 nv_error(priv,
236 "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
237 chid, nouveau_client_name(engctx), subc, class, mthd,
238 data);
239 }
240
241 nouveau_engctx_put(engctx);
242 }
243
244 static int
nv20_graph_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)245 nv20_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
246 struct nouveau_oclass *oclass, void *data, u32 size,
247 struct nouveau_object **pobject)
248 {
249 struct nv20_graph_priv *priv;
250 int ret;
251
252 ret = nouveau_graph_create(parent, engine, oclass, true, &priv);
253 *pobject = nv_object(priv);
254 if (ret)
255 return ret;
256
257 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
258 NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
259 if (ret)
260 return ret;
261
262 nv_subdev(priv)->unit = 0x00001000;
263 nv_subdev(priv)->intr = nv20_graph_intr;
264 nv_engine(priv)->cclass = &nv20_graph_cclass;
265 nv_engine(priv)->sclass = nv20_graph_sclass;
266 nv_engine(priv)->tile_prog = nv20_graph_tile_prog;
267 return 0;
268 }
269
270 void
nv20_graph_dtor(struct nouveau_object * object)271 nv20_graph_dtor(struct nouveau_object *object)
272 {
273 struct nv20_graph_priv *priv = (void *)object;
274 nouveau_gpuobj_ref(NULL, &priv->ctxtab);
275 nouveau_graph_destroy(&priv->base);
276 }
277
278 int
nv20_graph_init(struct nouveau_object * object)279 nv20_graph_init(struct nouveau_object *object)
280 {
281 struct nouveau_engine *engine = nv_engine(object);
282 struct nv20_graph_priv *priv = (void *)engine;
283 struct nouveau_fb *pfb = nouveau_fb(object);
284 u32 tmp, vramsz;
285 int ret, i;
286
287 ret = nouveau_graph_init(&priv->base);
288 if (ret)
289 return ret;
290
291 nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4);
292
293 if (nv_device(priv)->chipset == 0x20) {
294 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
295 for (i = 0; i < 15; i++)
296 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
297 nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
298 } else {
299 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
300 for (i = 0; i < 32; i++)
301 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000);
302 nv_wait(priv, 0x400700, 0xffffffff, 0x00000000);
303 }
304
305 nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF);
306 nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
307
308 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
309 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000);
310 nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700);
311 nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
312 nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000);
313 nv_wr32(priv, 0x40009C , 0x00000040);
314
315 if (nv_device(priv)->chipset >= 0x25) {
316 nv_wr32(priv, 0x400890, 0x00a8cfff);
317 nv_wr32(priv, 0x400610, 0x304B1FB6);
318 nv_wr32(priv, 0x400B80, 0x1cbd3883);
319 nv_wr32(priv, 0x400B84, 0x44000000);
320 nv_wr32(priv, 0x400098, 0x40000080);
321 nv_wr32(priv, 0x400B88, 0x000000ff);
322
323 } else {
324 nv_wr32(priv, 0x400880, 0x0008c7df);
325 nv_wr32(priv, 0x400094, 0x00000005);
326 nv_wr32(priv, 0x400B80, 0x45eae20e);
327 nv_wr32(priv, 0x400B84, 0x24000000);
328 nv_wr32(priv, 0x400098, 0x00000040);
329 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
330 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
331 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
332 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030);
333 }
334
335 /* Turn all the tiling regions off. */
336 for (i = 0; i < pfb->tile.regions; i++)
337 engine->tile_prog(engine, i);
338
339 nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324));
340 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
341 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324));
342
343 nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
344 nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF);
345
346 tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00;
347 nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
348 tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) | 0x00020100;
349 nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp);
350
351 /* begin RAM config */
352 vramsz = pci_resource_len(nv_device(priv)->pdev, 0) - 1;
353 nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200));
354 nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204));
355 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
356 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200));
357 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
358 nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204));
359 nv_wr32(priv, 0x400820, 0);
360 nv_wr32(priv, 0x400824, 0);
361 nv_wr32(priv, 0x400864, vramsz - 1);
362 nv_wr32(priv, 0x400868, vramsz - 1);
363
364 /* interesting.. the below overwrites some of the tile setup above.. */
365 nv_wr32(priv, 0x400B20, 0x00000000);
366 nv_wr32(priv, 0x400B04, 0xFFFFFFFF);
367
368 nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
369 nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
370 nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
371 nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
372 return 0;
373 }
374
375 struct nouveau_oclass
376 nv20_graph_oclass = {
377 .handle = NV_ENGINE(GR, 0x20),
378 .ofuncs = &(struct nouveau_ofuncs) {
379 .ctor = nv20_graph_ctor,
380 .dtor = nv20_graph_dtor,
381 .init = nv20_graph_init,
382 .fini = _nouveau_graph_fini,
383 },
384 };
385