1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <core/gpuobj.h>
26
27 #include <subdev/timer.h>
28 #include <subdev/bar.h>
29 #include <subdev/fb.h>
30 #include <subdev/vm.h>
31
32 struct nv50_bar_priv {
33 struct nouveau_bar base;
34 spinlock_t lock;
35 struct nouveau_gpuobj *mem;
36 struct nouveau_gpuobj *pad;
37 struct nouveau_gpuobj *pgd;
38 struct nouveau_vm *bar1_vm;
39 struct nouveau_gpuobj *bar1;
40 struct nouveau_vm *bar3_vm;
41 struct nouveau_gpuobj *bar3;
42 };
43
44 static int
nv50_bar_kmap(struct nouveau_bar * bar,struct nouveau_mem * mem,u32 flags,struct nouveau_vma * vma)45 nv50_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem,
46 u32 flags, struct nouveau_vma *vma)
47 {
48 struct nv50_bar_priv *priv = (void *)bar;
49 int ret;
50
51 ret = nouveau_vm_get(priv->bar3_vm, mem->size << 12, 12, flags, vma);
52 if (ret)
53 return ret;
54
55 nouveau_vm_map(vma, mem);
56 nv50_vm_flush_engine(nv_subdev(bar), 6);
57 return 0;
58 }
59
60 static int
nv50_bar_umap(struct nouveau_bar * bar,struct nouveau_mem * mem,u32 flags,struct nouveau_vma * vma)61 nv50_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem,
62 u32 flags, struct nouveau_vma *vma)
63 {
64 struct nv50_bar_priv *priv = (void *)bar;
65 int ret;
66
67 ret = nouveau_vm_get(priv->bar1_vm, mem->size << 12, 12, flags, vma);
68 if (ret)
69 return ret;
70
71 nouveau_vm_map(vma, mem);
72 nv50_vm_flush_engine(nv_subdev(bar), 6);
73 return 0;
74 }
75
76 static void
nv50_bar_unmap(struct nouveau_bar * bar,struct nouveau_vma * vma)77 nv50_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma)
78 {
79 nouveau_vm_unmap(vma);
80 nv50_vm_flush_engine(nv_subdev(bar), 6);
81 nouveau_vm_put(vma);
82 }
83
84 static void
nv50_bar_flush(struct nouveau_bar * bar)85 nv50_bar_flush(struct nouveau_bar *bar)
86 {
87 struct nv50_bar_priv *priv = (void *)bar;
88 unsigned long flags;
89 spin_lock_irqsave(&priv->lock, flags);
90 nv_wr32(priv, 0x00330c, 0x00000001);
91 if (!nv_wait(priv, 0x00330c, 0x00000002, 0x00000000))
92 nv_warn(priv, "flush timeout\n");
93 spin_unlock_irqrestore(&priv->lock, flags);
94 }
95
96 void
nv84_bar_flush(struct nouveau_bar * bar)97 nv84_bar_flush(struct nouveau_bar *bar)
98 {
99 struct nv50_bar_priv *priv = (void *)bar;
100 unsigned long flags;
101 spin_lock_irqsave(&priv->lock, flags);
102 nv_wr32(bar, 0x070000, 0x00000001);
103 if (!nv_wait(priv, 0x070000, 0x00000002, 0x00000000))
104 nv_warn(priv, "flush timeout\n");
105 spin_unlock_irqrestore(&priv->lock, flags);
106 }
107
108 static int
nv50_bar_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)109 nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
110 struct nouveau_oclass *oclass, void *data, u32 size,
111 struct nouveau_object **pobject)
112 {
113 struct nouveau_device *device = nv_device(parent);
114 struct nouveau_object *heap;
115 struct nouveau_vm *vm;
116 struct nv50_bar_priv *priv;
117 u64 start, limit;
118 int ret;
119
120 ret = nouveau_bar_create(parent, engine, oclass, &priv);
121 *pobject = nv_object(priv);
122 if (ret)
123 return ret;
124
125 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x20000, 0,
126 NVOBJ_FLAG_HEAP, &priv->mem);
127 heap = nv_object(priv->mem);
128 if (ret)
129 return ret;
130
131 ret = nouveau_gpuobj_new(nv_object(priv), heap,
132 (device->chipset == 0x50) ? 0x1400 : 0x0200,
133 0, 0, &priv->pad);
134 if (ret)
135 return ret;
136
137 ret = nouveau_gpuobj_new(nv_object(priv), heap, 0x4000, 0,
138 0, &priv->pgd);
139 if (ret)
140 return ret;
141
142 /* BAR3 */
143 start = 0x0100000000ULL;
144 limit = start + pci_resource_len(device->pdev, 3);
145
146 ret = nouveau_vm_new(device, start, limit, start, &vm);
147 if (ret)
148 return ret;
149
150 ret = nouveau_gpuobj_new(nv_object(priv), heap,
151 ((limit-- - start) >> 12) * 8, 0x1000,
152 NVOBJ_FLAG_ZERO_ALLOC, &vm->pgt[0].obj[0]);
153 vm->pgt[0].refcount[0] = 1;
154 if (ret)
155 return ret;
156
157 ret = nouveau_vm_ref(vm, &priv->bar3_vm, priv->pgd);
158 nouveau_vm_ref(NULL, &vm, NULL);
159 if (ret)
160 return ret;
161
162 ret = nouveau_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar3);
163 if (ret)
164 return ret;
165
166 nv_wo32(priv->bar3, 0x00, 0x7fc00000);
167 nv_wo32(priv->bar3, 0x04, lower_32_bits(limit));
168 nv_wo32(priv->bar3, 0x08, lower_32_bits(start));
169 nv_wo32(priv->bar3, 0x0c, upper_32_bits(limit) << 24 |
170 upper_32_bits(start));
171 nv_wo32(priv->bar3, 0x10, 0x00000000);
172 nv_wo32(priv->bar3, 0x14, 0x00000000);
173
174 /* BAR1 */
175 start = 0x0000000000ULL;
176 limit = start + pci_resource_len(device->pdev, 1);
177
178 ret = nouveau_vm_new(device, start, limit--, start, &vm);
179 if (ret)
180 return ret;
181
182 ret = nouveau_vm_ref(vm, &priv->bar1_vm, priv->pgd);
183 nouveau_vm_ref(NULL, &vm, NULL);
184 if (ret)
185 return ret;
186
187 ret = nouveau_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar1);
188 if (ret)
189 return ret;
190
191 nv_wo32(priv->bar1, 0x00, 0x7fc00000);
192 nv_wo32(priv->bar1, 0x04, lower_32_bits(limit));
193 nv_wo32(priv->bar1, 0x08, lower_32_bits(start));
194 nv_wo32(priv->bar1, 0x0c, upper_32_bits(limit) << 24 |
195 upper_32_bits(start));
196 nv_wo32(priv->bar1, 0x10, 0x00000000);
197 nv_wo32(priv->bar1, 0x14, 0x00000000);
198
199 priv->base.alloc = nouveau_bar_alloc;
200 priv->base.kmap = nv50_bar_kmap;
201 priv->base.umap = nv50_bar_umap;
202 priv->base.unmap = nv50_bar_unmap;
203 if (device->chipset == 0x50)
204 priv->base.flush = nv50_bar_flush;
205 else
206 priv->base.flush = nv84_bar_flush;
207 spin_lock_init(&priv->lock);
208 return 0;
209 }
210
211 static void
nv50_bar_dtor(struct nouveau_object * object)212 nv50_bar_dtor(struct nouveau_object *object)
213 {
214 struct nv50_bar_priv *priv = (void *)object;
215 nouveau_gpuobj_ref(NULL, &priv->bar1);
216 nouveau_vm_ref(NULL, &priv->bar1_vm, priv->pgd);
217 nouveau_gpuobj_ref(NULL, &priv->bar3);
218 if (priv->bar3_vm) {
219 nouveau_gpuobj_ref(NULL, &priv->bar3_vm->pgt[0].obj[0]);
220 nouveau_vm_ref(NULL, &priv->bar3_vm, priv->pgd);
221 }
222 nouveau_gpuobj_ref(NULL, &priv->pgd);
223 nouveau_gpuobj_ref(NULL, &priv->pad);
224 nouveau_gpuobj_ref(NULL, &priv->mem);
225 nouveau_bar_destroy(&priv->base);
226 }
227
228 static int
nv50_bar_init(struct nouveau_object * object)229 nv50_bar_init(struct nouveau_object *object)
230 {
231 struct nv50_bar_priv *priv = (void *)object;
232 int ret;
233
234 ret = nouveau_bar_init(&priv->base);
235 if (ret)
236 return ret;
237
238 nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
239 nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
240 nv50_vm_flush_engine(nv_subdev(priv), 6);
241
242 nv_wr32(priv, 0x001704, 0x00000000 | priv->mem->addr >> 12);
243 nv_wr32(priv, 0x001704, 0x40000000 | priv->mem->addr >> 12);
244 nv_wr32(priv, 0x001708, 0x80000000 | priv->bar1->node->offset >> 4);
245 nv_wr32(priv, 0x00170c, 0x80000000 | priv->bar3->node->offset >> 4);
246 return 0;
247 }
248
249 static int
nv50_bar_fini(struct nouveau_object * object,bool suspend)250 nv50_bar_fini(struct nouveau_object *object, bool suspend)
251 {
252 struct nv50_bar_priv *priv = (void *)object;
253 return nouveau_bar_fini(&priv->base, suspend);
254 }
255
256 struct nouveau_oclass
257 nv50_bar_oclass = {
258 .handle = NV_SUBDEV(BAR, 0x50),
259 .ofuncs = &(struct nouveau_ofuncs) {
260 .ctor = nv50_bar_ctor,
261 .dtor = nv50_bar_dtor,
262 .init = nv50_bar_init,
263 .fini = nv50_bar_fini,
264 },
265 };
266