1 /*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
12 *
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
24
25 #include <asm/tlb.h>
26 #include <asm/mach/map.h>
27
28 #include <linux/omap-dma.h>
29
30 #include "omap_hwmod.h"
31 #include "soc.h"
32 #include "iomap.h"
33 #include "voltage.h"
34 #include "powerdomain.h"
35 #include "clockdomain.h"
36 #include "common.h"
37 #include "clock.h"
38 #include "clock2xxx.h"
39 #include "clock3xxx.h"
40 #include "clock44xx.h"
41 #include "omap-pm.h"
42 #include "sdrc.h"
43 #include "control.h"
44 #include "serial.h"
45 #include "sram.h"
46 #include "cm2xxx.h"
47 #include "cm3xxx.h"
48 #include "prm.h"
49 #include "cm.h"
50 #include "prcm_mpu44xx.h"
51 #include "prminst44xx.h"
52 #include "cminst44xx.h"
53 #include "prm2xxx.h"
54 #include "prm3xxx.h"
55 #include "prm44xx.h"
56
57 /*
58 * omap_clk_init: points to a function that does the SoC-specific
59 * clock initializations
60 */
61 int (*omap_clk_init)(void);
62
63 /*
64 * The machine specific code may provide the extra mapping besides the
65 * default mapping provided here.
66 */
67
68 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
69 static struct map_desc omap24xx_io_desc[] __initdata = {
70 {
71 .virtual = L3_24XX_VIRT,
72 .pfn = __phys_to_pfn(L3_24XX_PHYS),
73 .length = L3_24XX_SIZE,
74 .type = MT_DEVICE
75 },
76 {
77 .virtual = L4_24XX_VIRT,
78 .pfn = __phys_to_pfn(L4_24XX_PHYS),
79 .length = L4_24XX_SIZE,
80 .type = MT_DEVICE
81 },
82 };
83
84 #ifdef CONFIG_SOC_OMAP2420
85 static struct map_desc omap242x_io_desc[] __initdata = {
86 {
87 .virtual = DSP_MEM_2420_VIRT,
88 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
89 .length = DSP_MEM_2420_SIZE,
90 .type = MT_DEVICE
91 },
92 {
93 .virtual = DSP_IPI_2420_VIRT,
94 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
95 .length = DSP_IPI_2420_SIZE,
96 .type = MT_DEVICE
97 },
98 {
99 .virtual = DSP_MMU_2420_VIRT,
100 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
101 .length = DSP_MMU_2420_SIZE,
102 .type = MT_DEVICE
103 },
104 };
105
106 #endif
107
108 #ifdef CONFIG_SOC_OMAP2430
109 static struct map_desc omap243x_io_desc[] __initdata = {
110 {
111 .virtual = L4_WK_243X_VIRT,
112 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
113 .length = L4_WK_243X_SIZE,
114 .type = MT_DEVICE
115 },
116 {
117 .virtual = OMAP243X_GPMC_VIRT,
118 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
119 .length = OMAP243X_GPMC_SIZE,
120 .type = MT_DEVICE
121 },
122 {
123 .virtual = OMAP243X_SDRC_VIRT,
124 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
125 .length = OMAP243X_SDRC_SIZE,
126 .type = MT_DEVICE
127 },
128 {
129 .virtual = OMAP243X_SMS_VIRT,
130 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
131 .length = OMAP243X_SMS_SIZE,
132 .type = MT_DEVICE
133 },
134 };
135 #endif
136 #endif
137
138 #ifdef CONFIG_ARCH_OMAP3
139 static struct map_desc omap34xx_io_desc[] __initdata = {
140 {
141 .virtual = L3_34XX_VIRT,
142 .pfn = __phys_to_pfn(L3_34XX_PHYS),
143 .length = L3_34XX_SIZE,
144 .type = MT_DEVICE
145 },
146 {
147 .virtual = L4_34XX_VIRT,
148 .pfn = __phys_to_pfn(L4_34XX_PHYS),
149 .length = L4_34XX_SIZE,
150 .type = MT_DEVICE
151 },
152 {
153 .virtual = OMAP34XX_GPMC_VIRT,
154 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
155 .length = OMAP34XX_GPMC_SIZE,
156 .type = MT_DEVICE
157 },
158 {
159 .virtual = OMAP343X_SMS_VIRT,
160 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
161 .length = OMAP343X_SMS_SIZE,
162 .type = MT_DEVICE
163 },
164 {
165 .virtual = OMAP343X_SDRC_VIRT,
166 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
167 .length = OMAP343X_SDRC_SIZE,
168 .type = MT_DEVICE
169 },
170 {
171 .virtual = L4_PER_34XX_VIRT,
172 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
173 .length = L4_PER_34XX_SIZE,
174 .type = MT_DEVICE
175 },
176 {
177 .virtual = L4_EMU_34XX_VIRT,
178 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
179 .length = L4_EMU_34XX_SIZE,
180 .type = MT_DEVICE
181 },
182 #if defined(CONFIG_DEBUG_LL) && \
183 (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
184 {
185 .virtual = ZOOM_UART_VIRT,
186 .pfn = __phys_to_pfn(ZOOM_UART_BASE),
187 .length = SZ_1M,
188 .type = MT_DEVICE
189 },
190 #endif
191 };
192 #endif
193
194 #ifdef CONFIG_SOC_TI81XX
195 static struct map_desc omapti81xx_io_desc[] __initdata = {
196 {
197 .virtual = L4_34XX_VIRT,
198 .pfn = __phys_to_pfn(L4_34XX_PHYS),
199 .length = L4_34XX_SIZE,
200 .type = MT_DEVICE
201 }
202 };
203 #endif
204
205 #ifdef CONFIG_SOC_AM33XX
206 static struct map_desc omapam33xx_io_desc[] __initdata = {
207 {
208 .virtual = L4_34XX_VIRT,
209 .pfn = __phys_to_pfn(L4_34XX_PHYS),
210 .length = L4_34XX_SIZE,
211 .type = MT_DEVICE
212 },
213 {
214 .virtual = L4_WK_AM33XX_VIRT,
215 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
216 .length = L4_WK_AM33XX_SIZE,
217 .type = MT_DEVICE
218 }
219 };
220 #endif
221
222 #ifdef CONFIG_ARCH_OMAP4
223 static struct map_desc omap44xx_io_desc[] __initdata = {
224 {
225 .virtual = L3_44XX_VIRT,
226 .pfn = __phys_to_pfn(L3_44XX_PHYS),
227 .length = L3_44XX_SIZE,
228 .type = MT_DEVICE,
229 },
230 {
231 .virtual = L4_44XX_VIRT,
232 .pfn = __phys_to_pfn(L4_44XX_PHYS),
233 .length = L4_44XX_SIZE,
234 .type = MT_DEVICE,
235 },
236 {
237 .virtual = L4_PER_44XX_VIRT,
238 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
239 .length = L4_PER_44XX_SIZE,
240 .type = MT_DEVICE,
241 },
242 #ifdef CONFIG_OMAP4_ERRATA_I688
243 {
244 .virtual = OMAP4_SRAM_VA,
245 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
246 .length = PAGE_SIZE,
247 .type = MT_MEMORY_SO,
248 },
249 #endif
250
251 };
252 #endif
253
254 #ifdef CONFIG_SOC_OMAP5
255 static struct map_desc omap54xx_io_desc[] __initdata = {
256 {
257 .virtual = L3_54XX_VIRT,
258 .pfn = __phys_to_pfn(L3_54XX_PHYS),
259 .length = L3_54XX_SIZE,
260 .type = MT_DEVICE,
261 },
262 {
263 .virtual = L4_54XX_VIRT,
264 .pfn = __phys_to_pfn(L4_54XX_PHYS),
265 .length = L4_54XX_SIZE,
266 .type = MT_DEVICE,
267 },
268 {
269 .virtual = L4_WK_54XX_VIRT,
270 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
271 .length = L4_WK_54XX_SIZE,
272 .type = MT_DEVICE,
273 },
274 {
275 .virtual = L4_PER_54XX_VIRT,
276 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
277 .length = L4_PER_54XX_SIZE,
278 .type = MT_DEVICE,
279 },
280 #ifdef CONFIG_OMAP4_ERRATA_I688
281 {
282 .virtual = OMAP4_SRAM_VA,
283 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
284 .length = PAGE_SIZE,
285 .type = MT_MEMORY_SO,
286 },
287 #endif
288 };
289 #endif
290
291 #ifdef CONFIG_SOC_OMAP2420
omap242x_map_io(void)292 void __init omap242x_map_io(void)
293 {
294 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
295 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
296 }
297 #endif
298
299 #ifdef CONFIG_SOC_OMAP2430
omap243x_map_io(void)300 void __init omap243x_map_io(void)
301 {
302 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
303 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
304 }
305 #endif
306
307 #ifdef CONFIG_ARCH_OMAP3
omap3_map_io(void)308 void __init omap3_map_io(void)
309 {
310 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
311 }
312 #endif
313
314 #ifdef CONFIG_SOC_TI81XX
ti81xx_map_io(void)315 void __init ti81xx_map_io(void)
316 {
317 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
318 }
319 #endif
320
321 #ifdef CONFIG_SOC_AM33XX
am33xx_map_io(void)322 void __init am33xx_map_io(void)
323 {
324 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
325 }
326 #endif
327
328 #ifdef CONFIG_ARCH_OMAP4
omap4_map_io(void)329 void __init omap4_map_io(void)
330 {
331 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
332 omap_barriers_init();
333 }
334 #endif
335
336 #ifdef CONFIG_SOC_OMAP5
omap5_map_io(void)337 void __init omap5_map_io(void)
338 {
339 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
340 omap_barriers_init();
341 }
342 #endif
343 /*
344 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
345 *
346 * Sets the CORE DPLL3 M2 divider to the same value that it's at
347 * currently. This has the effect of setting the SDRC SDRAM AC timing
348 * registers to the values currently defined by the kernel. Currently
349 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
350 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
351 * or passes along the return value of clk_set_rate().
352 */
_omap2_init_reprogram_sdrc(void)353 static int __init _omap2_init_reprogram_sdrc(void)
354 {
355 struct clk *dpll3_m2_ck;
356 int v = -EINVAL;
357 long rate;
358
359 if (!cpu_is_omap34xx())
360 return 0;
361
362 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
363 if (IS_ERR(dpll3_m2_ck))
364 return -EINVAL;
365
366 rate = clk_get_rate(dpll3_m2_ck);
367 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
368 v = clk_set_rate(dpll3_m2_ck, rate);
369 if (v)
370 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
371
372 clk_put(dpll3_m2_ck);
373
374 return v;
375 }
376
_set_hwmod_postsetup_state(struct omap_hwmod * oh,void * data)377 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
378 {
379 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
380 }
381
omap_hwmod_init_postsetup(void)382 static void __init omap_hwmod_init_postsetup(void)
383 {
384 u8 postsetup_state;
385
386 /* Set the default postsetup state for all hwmods */
387 #ifdef CONFIG_PM_RUNTIME
388 postsetup_state = _HWMOD_STATE_IDLE;
389 #else
390 postsetup_state = _HWMOD_STATE_ENABLED;
391 #endif
392 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
393
394 omap_pm_if_early_init();
395 }
396
omap_common_late_init(void)397 static void __init omap_common_late_init(void)
398 {
399 omap_mux_late_init();
400 omap2_common_pm_late_init();
401 omap_soc_device_init();
402 }
403
404 #ifdef CONFIG_SOC_OMAP2420
omap2420_init_early(void)405 void __init omap2420_init_early(void)
406 {
407 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
408 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
409 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
410 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
411 NULL);
412 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
413 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
414 omap2xxx_check_revision();
415 omap2xxx_prm_init();
416 omap2xxx_cm_init();
417 omap2xxx_voltagedomains_init();
418 omap242x_powerdomains_init();
419 omap242x_clockdomains_init();
420 omap2420_hwmod_init();
421 omap_hwmod_init_postsetup();
422 omap_clk_init = omap2420_clk_init;
423 }
424
omap2420_init_late(void)425 void __init omap2420_init_late(void)
426 {
427 omap_common_late_init();
428 omap2_pm_init();
429 omap2_clk_enable_autoidle_all();
430 }
431 #endif
432
433 #ifdef CONFIG_SOC_OMAP2430
omap2430_init_early(void)434 void __init omap2430_init_early(void)
435 {
436 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
437 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
438 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
439 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
440 NULL);
441 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
442 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
443 omap2xxx_check_revision();
444 omap2xxx_prm_init();
445 omap2xxx_cm_init();
446 omap2xxx_voltagedomains_init();
447 omap243x_powerdomains_init();
448 omap243x_clockdomains_init();
449 omap2430_hwmod_init();
450 omap_hwmod_init_postsetup();
451 omap_clk_init = omap2430_clk_init;
452 }
453
omap2430_init_late(void)454 void __init omap2430_init_late(void)
455 {
456 omap_common_late_init();
457 omap2_pm_init();
458 omap2_clk_enable_autoidle_all();
459 }
460 #endif
461
462 /*
463 * Currently only board-omap3beagle.c should call this because of the
464 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
465 */
466 #ifdef CONFIG_ARCH_OMAP3
omap3_init_early(void)467 void __init omap3_init_early(void)
468 {
469 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
470 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
471 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
472 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
473 NULL);
474 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
475 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
476 omap3xxx_check_revision();
477 omap3xxx_check_features();
478 omap3xxx_prm_init();
479 omap3xxx_cm_init();
480 omap3xxx_voltagedomains_init();
481 omap3xxx_powerdomains_init();
482 omap3xxx_clockdomains_init();
483 omap3xxx_hwmod_init();
484 omap_hwmod_init_postsetup();
485 omap_clk_init = omap3xxx_clk_init;
486 }
487
omap3430_init_early(void)488 void __init omap3430_init_early(void)
489 {
490 omap3_init_early();
491 }
492
omap35xx_init_early(void)493 void __init omap35xx_init_early(void)
494 {
495 omap3_init_early();
496 }
497
omap3630_init_early(void)498 void __init omap3630_init_early(void)
499 {
500 omap3_init_early();
501 }
502
am35xx_init_early(void)503 void __init am35xx_init_early(void)
504 {
505 omap3_init_early();
506 }
507
ti81xx_init_early(void)508 void __init ti81xx_init_early(void)
509 {
510 omap2_set_globals_tap(OMAP343X_CLASS,
511 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
512 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
513 NULL);
514 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
515 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
516 omap3xxx_check_revision();
517 ti81xx_check_features();
518 omap3xxx_voltagedomains_init();
519 omap3xxx_powerdomains_init();
520 omap3xxx_clockdomains_init();
521 omap3xxx_hwmod_init();
522 omap_hwmod_init_postsetup();
523 omap_clk_init = omap3xxx_clk_init;
524 }
525
omap3_init_late(void)526 void __init omap3_init_late(void)
527 {
528 omap_common_late_init();
529 omap3_pm_init();
530 omap2_clk_enable_autoidle_all();
531 }
532
omap3430_init_late(void)533 void __init omap3430_init_late(void)
534 {
535 omap_common_late_init();
536 omap3_pm_init();
537 omap2_clk_enable_autoidle_all();
538 }
539
omap35xx_init_late(void)540 void __init omap35xx_init_late(void)
541 {
542 omap_common_late_init();
543 omap3_pm_init();
544 omap2_clk_enable_autoidle_all();
545 }
546
omap3630_init_late(void)547 void __init omap3630_init_late(void)
548 {
549 omap_common_late_init();
550 omap3_pm_init();
551 omap2_clk_enable_autoidle_all();
552 }
553
am35xx_init_late(void)554 void __init am35xx_init_late(void)
555 {
556 omap_common_late_init();
557 omap3_pm_init();
558 omap2_clk_enable_autoidle_all();
559 }
560
ti81xx_init_late(void)561 void __init ti81xx_init_late(void)
562 {
563 omap_common_late_init();
564 omap3_pm_init();
565 omap2_clk_enable_autoidle_all();
566 }
567 #endif
568
569 #ifdef CONFIG_SOC_AM33XX
am33xx_init_early(void)570 void __init am33xx_init_early(void)
571 {
572 omap2_set_globals_tap(AM335X_CLASS,
573 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
574 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
575 NULL);
576 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
577 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
578 omap3xxx_check_revision();
579 ti81xx_check_features();
580 am33xx_voltagedomains_init();
581 am33xx_powerdomains_init();
582 am33xx_clockdomains_init();
583 am33xx_hwmod_init();
584 omap_hwmod_init_postsetup();
585 omap_clk_init = am33xx_clk_init;
586 }
587 #endif
588
589 #ifdef CONFIG_ARCH_OMAP4
omap4430_init_early(void)590 void __init omap4430_init_early(void)
591 {
592 omap2_set_globals_tap(OMAP443X_CLASS,
593 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
594 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
595 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
596 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
597 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
598 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
599 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
600 omap_prm_base_init();
601 omap_cm_base_init();
602 omap4xxx_check_revision();
603 omap4xxx_check_features();
604 omap44xx_prm_init();
605 omap44xx_voltagedomains_init();
606 omap44xx_powerdomains_init();
607 omap44xx_clockdomains_init();
608 omap44xx_hwmod_init();
609 omap_hwmod_init_postsetup();
610 omap_clk_init = omap4xxx_clk_init;
611 }
612
omap4430_init_late(void)613 void __init omap4430_init_late(void)
614 {
615 omap_common_late_init();
616 omap4_pm_init();
617 omap2_clk_enable_autoidle_all();
618 }
619 #endif
620
621 #ifdef CONFIG_SOC_OMAP5
omap5_init_early(void)622 void __init omap5_init_early(void)
623 {
624 omap2_set_globals_tap(OMAP54XX_CLASS,
625 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
626 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
627 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
628 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
629 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
630 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
631 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
632 omap_prm_base_init();
633 omap_cm_base_init();
634 omap5xxx_check_revision();
635 }
636 #endif
637
omap_sdrc_init(struct omap_sdrc_params * sdrc_cs0,struct omap_sdrc_params * sdrc_cs1)638 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
639 struct omap_sdrc_params *sdrc_cs1)
640 {
641 omap_sram_init();
642
643 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
644 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
645 _omap2_init_reprogram_sdrc();
646 }
647 }
648