1 /*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 /*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <drm/drmP.h>
35 #include <drm/radeon_drm.h>
36 #include "radeon.h"
37 #include "radeon_trace.h"
38
39
40 int radeon_ttm_init(struct radeon_device *rdev);
41 void radeon_ttm_fini(struct radeon_device *rdev);
42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
43
44 /*
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
47 */
48
radeon_bo_clear_va(struct radeon_bo * bo)49 void radeon_bo_clear_va(struct radeon_bo *bo)
50 {
51 struct radeon_bo_va *bo_va, *tmp;
52
53 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
54 /* remove from all vm address space */
55 radeon_vm_bo_rmv(bo->rdev, bo_va);
56 }
57 }
58
radeon_ttm_bo_destroy(struct ttm_buffer_object * tbo)59 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
60 {
61 struct radeon_bo *bo;
62
63 bo = container_of(tbo, struct radeon_bo, tbo);
64 mutex_lock(&bo->rdev->gem.mutex);
65 list_del_init(&bo->list);
66 mutex_unlock(&bo->rdev->gem.mutex);
67 radeon_bo_clear_surface_reg(bo);
68 radeon_bo_clear_va(bo);
69 drm_gem_object_release(&bo->gem_base);
70 kfree(bo);
71 }
72
radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object * bo)73 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
74 {
75 if (bo->destroy == &radeon_ttm_bo_destroy)
76 return true;
77 return false;
78 }
79
radeon_ttm_placement_from_domain(struct radeon_bo * rbo,u32 domain)80 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
81 {
82 u32 c = 0;
83
84 rbo->placement.fpfn = 0;
85 rbo->placement.lpfn = 0;
86 rbo->placement.placement = rbo->placements;
87 rbo->placement.busy_placement = rbo->placements;
88 if (domain & RADEON_GEM_DOMAIN_VRAM)
89 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
90 TTM_PL_FLAG_VRAM;
91 if (domain & RADEON_GEM_DOMAIN_GTT) {
92 if (rbo->rdev->flags & RADEON_IS_AGP) {
93 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
94 } else {
95 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
96 }
97 }
98 if (domain & RADEON_GEM_DOMAIN_CPU) {
99 if (rbo->rdev->flags & RADEON_IS_AGP) {
100 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
101 } else {
102 rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
103 }
104 }
105 if (!c)
106 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
107 rbo->placement.num_placement = c;
108 rbo->placement.num_busy_placement = c;
109 }
110
radeon_bo_create(struct radeon_device * rdev,unsigned long size,int byte_align,bool kernel,u32 domain,struct sg_table * sg,struct radeon_bo ** bo_ptr)111 int radeon_bo_create(struct radeon_device *rdev,
112 unsigned long size, int byte_align, bool kernel, u32 domain,
113 struct sg_table *sg, struct radeon_bo **bo_ptr)
114 {
115 struct radeon_bo *bo;
116 enum ttm_bo_type type;
117 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
118 size_t acc_size;
119 int r;
120
121 size = ALIGN(size, PAGE_SIZE);
122
123 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
124 if (kernel) {
125 type = ttm_bo_type_kernel;
126 } else if (sg) {
127 type = ttm_bo_type_sg;
128 } else {
129 type = ttm_bo_type_device;
130 }
131 *bo_ptr = NULL;
132
133 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
134 sizeof(struct radeon_bo));
135
136 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
137 if (bo == NULL)
138 return -ENOMEM;
139 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
140 if (unlikely(r)) {
141 kfree(bo);
142 return r;
143 }
144 bo->rdev = rdev;
145 bo->gem_base.driver_private = NULL;
146 bo->surface_reg = -1;
147 INIT_LIST_HEAD(&bo->list);
148 INIT_LIST_HEAD(&bo->va);
149 radeon_ttm_placement_from_domain(bo, domain);
150 /* Kernel allocation are uninterruptible */
151 down_read(&rdev->pm.mclk_lock);
152 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
153 &bo->placement, page_align, !kernel, NULL,
154 acc_size, sg, &radeon_ttm_bo_destroy);
155 up_read(&rdev->pm.mclk_lock);
156 if (unlikely(r != 0)) {
157 return r;
158 }
159 *bo_ptr = bo;
160
161 trace_radeon_bo_create(bo);
162
163 return 0;
164 }
165
radeon_bo_kmap(struct radeon_bo * bo,void ** ptr)166 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
167 {
168 bool is_iomem;
169 int r;
170
171 if (bo->kptr) {
172 if (ptr) {
173 *ptr = bo->kptr;
174 }
175 return 0;
176 }
177 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
178 if (r) {
179 return r;
180 }
181 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
182 if (ptr) {
183 *ptr = bo->kptr;
184 }
185 radeon_bo_check_tiling(bo, 0, 0);
186 return 0;
187 }
188
radeon_bo_kunmap(struct radeon_bo * bo)189 void radeon_bo_kunmap(struct radeon_bo *bo)
190 {
191 if (bo->kptr == NULL)
192 return;
193 bo->kptr = NULL;
194 radeon_bo_check_tiling(bo, 0, 0);
195 ttm_bo_kunmap(&bo->kmap);
196 }
197
radeon_bo_unref(struct radeon_bo ** bo)198 void radeon_bo_unref(struct radeon_bo **bo)
199 {
200 struct ttm_buffer_object *tbo;
201 struct radeon_device *rdev;
202
203 if ((*bo) == NULL)
204 return;
205 rdev = (*bo)->rdev;
206 tbo = &((*bo)->tbo);
207 down_read(&rdev->pm.mclk_lock);
208 ttm_bo_unref(&tbo);
209 up_read(&rdev->pm.mclk_lock);
210 if (tbo == NULL)
211 *bo = NULL;
212 }
213
radeon_bo_pin_restricted(struct radeon_bo * bo,u32 domain,u64 max_offset,u64 * gpu_addr)214 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
215 u64 *gpu_addr)
216 {
217 int r, i;
218
219 if (bo->pin_count) {
220 bo->pin_count++;
221 if (gpu_addr)
222 *gpu_addr = radeon_bo_gpu_offset(bo);
223
224 if (max_offset != 0) {
225 u64 domain_start;
226
227 if (domain == RADEON_GEM_DOMAIN_VRAM)
228 domain_start = bo->rdev->mc.vram_start;
229 else
230 domain_start = bo->rdev->mc.gtt_start;
231 WARN_ON_ONCE(max_offset <
232 (radeon_bo_gpu_offset(bo) - domain_start));
233 }
234
235 return 0;
236 }
237 radeon_ttm_placement_from_domain(bo, domain);
238 if (domain == RADEON_GEM_DOMAIN_VRAM) {
239 /* force to pin into visible video ram */
240 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
241 }
242 if (max_offset) {
243 u64 lpfn = max_offset >> PAGE_SHIFT;
244
245 if (!bo->placement.lpfn)
246 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
247
248 if (lpfn < bo->placement.lpfn)
249 bo->placement.lpfn = lpfn;
250 }
251 for (i = 0; i < bo->placement.num_placement; i++)
252 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
253 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
254 if (likely(r == 0)) {
255 bo->pin_count = 1;
256 if (gpu_addr != NULL)
257 *gpu_addr = radeon_bo_gpu_offset(bo);
258 }
259 if (unlikely(r != 0))
260 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
261 return r;
262 }
263
radeon_bo_pin(struct radeon_bo * bo,u32 domain,u64 * gpu_addr)264 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
265 {
266 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
267 }
268
radeon_bo_unpin(struct radeon_bo * bo)269 int radeon_bo_unpin(struct radeon_bo *bo)
270 {
271 int r, i;
272
273 if (!bo->pin_count) {
274 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
275 return 0;
276 }
277 bo->pin_count--;
278 if (bo->pin_count)
279 return 0;
280 for (i = 0; i < bo->placement.num_placement; i++)
281 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
282 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
283 if (unlikely(r != 0))
284 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
285 return r;
286 }
287
radeon_bo_evict_vram(struct radeon_device * rdev)288 int radeon_bo_evict_vram(struct radeon_device *rdev)
289 {
290 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
291 if (0 && (rdev->flags & RADEON_IS_IGP)) {
292 if (rdev->mc.igp_sideport_enabled == false)
293 /* Useless to evict on IGP chips */
294 return 0;
295 }
296 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
297 }
298
radeon_bo_force_delete(struct radeon_device * rdev)299 void radeon_bo_force_delete(struct radeon_device *rdev)
300 {
301 struct radeon_bo *bo, *n;
302
303 if (list_empty(&rdev->gem.objects)) {
304 return;
305 }
306 dev_err(rdev->dev, "Userspace still has active objects !\n");
307 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
308 mutex_lock(&rdev->ddev->struct_mutex);
309 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
310 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
311 *((unsigned long *)&bo->gem_base.refcount));
312 mutex_lock(&bo->rdev->gem.mutex);
313 list_del_init(&bo->list);
314 mutex_unlock(&bo->rdev->gem.mutex);
315 /* this should unref the ttm bo */
316 drm_gem_object_unreference(&bo->gem_base);
317 mutex_unlock(&rdev->ddev->struct_mutex);
318 }
319 }
320
radeon_bo_init(struct radeon_device * rdev)321 int radeon_bo_init(struct radeon_device *rdev)
322 {
323 /* Add an MTRR for the VRAM */
324 if (!rdev->fastfb_working) {
325 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
326 MTRR_TYPE_WRCOMB, 1);
327 }
328 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
329 rdev->mc.mc_vram_size >> 20,
330 (unsigned long long)rdev->mc.aper_size >> 20);
331 DRM_INFO("RAM width %dbits %cDR\n",
332 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
333 return radeon_ttm_init(rdev);
334 }
335
radeon_bo_fini(struct radeon_device * rdev)336 void radeon_bo_fini(struct radeon_device *rdev)
337 {
338 radeon_ttm_fini(rdev);
339 }
340
radeon_bo_list_add_object(struct radeon_bo_list * lobj,struct list_head * head)341 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
342 struct list_head *head)
343 {
344 if (lobj->written) {
345 list_add(&lobj->tv.head, head);
346 } else {
347 list_add_tail(&lobj->tv.head, head);
348 }
349 }
350
radeon_bo_list_validate(struct list_head * head,int ring)351 int radeon_bo_list_validate(struct list_head *head, int ring)
352 {
353 struct radeon_bo_list *lobj;
354 struct radeon_bo *bo;
355 u32 domain;
356 int r;
357
358 r = ttm_eu_reserve_buffers(head);
359 if (unlikely(r != 0)) {
360 return r;
361 }
362 list_for_each_entry(lobj, head, tv.head) {
363 bo = lobj->bo;
364 if (!bo->pin_count) {
365 domain = lobj->domain;
366
367 retry:
368 radeon_ttm_placement_from_domain(bo, domain);
369 if (ring == R600_RING_TYPE_UVD_INDEX)
370 radeon_uvd_force_into_uvd_segment(bo);
371 r = ttm_bo_validate(&bo->tbo, &bo->placement,
372 true, false);
373 if (unlikely(r)) {
374 if (r != -ERESTARTSYS && domain != lobj->alt_domain) {
375 domain = lobj->alt_domain;
376 goto retry;
377 }
378 return r;
379 }
380 }
381 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
382 lobj->tiling_flags = bo->tiling_flags;
383 }
384 return 0;
385 }
386
radeon_bo_fbdev_mmap(struct radeon_bo * bo,struct vm_area_struct * vma)387 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
388 struct vm_area_struct *vma)
389 {
390 return ttm_fbdev_mmap(vma, &bo->tbo);
391 }
392
radeon_bo_get_surface_reg(struct radeon_bo * bo)393 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
394 {
395 struct radeon_device *rdev = bo->rdev;
396 struct radeon_surface_reg *reg;
397 struct radeon_bo *old_object;
398 int steal;
399 int i;
400
401 BUG_ON(!radeon_bo_is_reserved(bo));
402
403 if (!bo->tiling_flags)
404 return 0;
405
406 if (bo->surface_reg >= 0) {
407 reg = &rdev->surface_regs[bo->surface_reg];
408 i = bo->surface_reg;
409 goto out;
410 }
411
412 steal = -1;
413 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
414
415 reg = &rdev->surface_regs[i];
416 if (!reg->bo)
417 break;
418
419 old_object = reg->bo;
420 if (old_object->pin_count == 0)
421 steal = i;
422 }
423
424 /* if we are all out */
425 if (i == RADEON_GEM_MAX_SURFACES) {
426 if (steal == -1)
427 return -ENOMEM;
428 /* find someone with a surface reg and nuke their BO */
429 reg = &rdev->surface_regs[steal];
430 old_object = reg->bo;
431 /* blow away the mapping */
432 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
433 ttm_bo_unmap_virtual(&old_object->tbo);
434 old_object->surface_reg = -1;
435 i = steal;
436 }
437
438 bo->surface_reg = i;
439 reg->bo = bo;
440
441 out:
442 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
443 bo->tbo.mem.start << PAGE_SHIFT,
444 bo->tbo.num_pages << PAGE_SHIFT);
445 return 0;
446 }
447
radeon_bo_clear_surface_reg(struct radeon_bo * bo)448 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
449 {
450 struct radeon_device *rdev = bo->rdev;
451 struct radeon_surface_reg *reg;
452
453 if (bo->surface_reg == -1)
454 return;
455
456 reg = &rdev->surface_regs[bo->surface_reg];
457 radeon_clear_surface_reg(rdev, bo->surface_reg);
458
459 reg->bo = NULL;
460 bo->surface_reg = -1;
461 }
462
radeon_bo_set_tiling_flags(struct radeon_bo * bo,uint32_t tiling_flags,uint32_t pitch)463 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
464 uint32_t tiling_flags, uint32_t pitch)
465 {
466 struct radeon_device *rdev = bo->rdev;
467 int r;
468
469 if (rdev->family >= CHIP_CEDAR) {
470 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
471
472 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
473 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
474 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
475 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
476 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
477 switch (bankw) {
478 case 0:
479 case 1:
480 case 2:
481 case 4:
482 case 8:
483 break;
484 default:
485 return -EINVAL;
486 }
487 switch (bankh) {
488 case 0:
489 case 1:
490 case 2:
491 case 4:
492 case 8:
493 break;
494 default:
495 return -EINVAL;
496 }
497 switch (mtaspect) {
498 case 0:
499 case 1:
500 case 2:
501 case 4:
502 case 8:
503 break;
504 default:
505 return -EINVAL;
506 }
507 if (tilesplit > 6) {
508 return -EINVAL;
509 }
510 if (stilesplit > 6) {
511 return -EINVAL;
512 }
513 }
514 r = radeon_bo_reserve(bo, false);
515 if (unlikely(r != 0))
516 return r;
517 bo->tiling_flags = tiling_flags;
518 bo->pitch = pitch;
519 radeon_bo_unreserve(bo);
520 return 0;
521 }
522
radeon_bo_get_tiling_flags(struct radeon_bo * bo,uint32_t * tiling_flags,uint32_t * pitch)523 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
524 uint32_t *tiling_flags,
525 uint32_t *pitch)
526 {
527 BUG_ON(!radeon_bo_is_reserved(bo));
528 if (tiling_flags)
529 *tiling_flags = bo->tiling_flags;
530 if (pitch)
531 *pitch = bo->pitch;
532 }
533
radeon_bo_check_tiling(struct radeon_bo * bo,bool has_moved,bool force_drop)534 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
535 bool force_drop)
536 {
537 BUG_ON(!radeon_bo_is_reserved(bo) && !force_drop);
538
539 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
540 return 0;
541
542 if (force_drop) {
543 radeon_bo_clear_surface_reg(bo);
544 return 0;
545 }
546
547 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
548 if (!has_moved)
549 return 0;
550
551 if (bo->surface_reg >= 0)
552 radeon_bo_clear_surface_reg(bo);
553 return 0;
554 }
555
556 if ((bo->surface_reg >= 0) && !has_moved)
557 return 0;
558
559 return radeon_bo_get_surface_reg(bo);
560 }
561
radeon_bo_move_notify(struct ttm_buffer_object * bo,struct ttm_mem_reg * mem)562 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
563 struct ttm_mem_reg *mem)
564 {
565 struct radeon_bo *rbo;
566 if (!radeon_ttm_bo_is_radeon_bo(bo))
567 return;
568 rbo = container_of(bo, struct radeon_bo, tbo);
569 radeon_bo_check_tiling(rbo, 0, 1);
570 radeon_vm_bo_invalidate(rbo->rdev, rbo);
571 }
572
radeon_bo_fault_reserve_notify(struct ttm_buffer_object * bo)573 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
574 {
575 struct radeon_device *rdev;
576 struct radeon_bo *rbo;
577 unsigned long offset, size;
578 int r;
579
580 if (!radeon_ttm_bo_is_radeon_bo(bo))
581 return 0;
582 rbo = container_of(bo, struct radeon_bo, tbo);
583 radeon_bo_check_tiling(rbo, 0, 0);
584 rdev = rbo->rdev;
585 if (bo->mem.mem_type == TTM_PL_VRAM) {
586 size = bo->mem.num_pages << PAGE_SHIFT;
587 offset = bo->mem.start << PAGE_SHIFT;
588 if ((offset + size) > rdev->mc.visible_vram_size) {
589 /* hurrah the memory is not visible ! */
590 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
591 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
592 r = ttm_bo_validate(bo, &rbo->placement, false, false);
593 if (unlikely(r != 0))
594 return r;
595 offset = bo->mem.start << PAGE_SHIFT;
596 /* this should not happen */
597 if ((offset + size) > rdev->mc.visible_vram_size)
598 return -EINVAL;
599 }
600 }
601 return 0;
602 }
603
radeon_bo_wait(struct radeon_bo * bo,u32 * mem_type,bool no_wait)604 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
605 {
606 int r;
607
608 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
609 if (unlikely(r != 0))
610 return r;
611 spin_lock(&bo->tbo.bdev->fence_lock);
612 if (mem_type)
613 *mem_type = bo->tbo.mem.mem_type;
614 if (bo->tbo.sync_obj)
615 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
616 spin_unlock(&bo->tbo.bdev->fence_lock);
617 ttm_bo_unreserve(&bo->tbo);
618 return r;
619 }
620
621
622 /**
623 * radeon_bo_reserve - reserve bo
624 * @bo: bo structure
625 * @no_intr: don't return -ERESTARTSYS on pending signal
626 *
627 * Returns:
628 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
629 * a signal. Release all buffer reservations and return to user-space.
630 */
radeon_bo_reserve(struct radeon_bo * bo,bool no_intr)631 int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
632 {
633 int r;
634
635 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
636 if (unlikely(r != 0)) {
637 if (r != -ERESTARTSYS)
638 dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
639 return r;
640 }
641 return 0;
642 }
643