1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "wifi.h"
31 #include "core.h"
32 #include "pci.h"
33 #include "base.h"
34 #include "ps.h"
35 #include "efuse.h"
36 #include <linux/export.h>
37 #include <linux/kmemleak.h>
38
39 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
40 PCI_VENDOR_ID_INTEL,
41 PCI_VENDOR_ID_ATI,
42 PCI_VENDOR_ID_AMD,
43 PCI_VENDOR_ID_SI
44 };
45
46 static const u8 ac_to_hwq[] = {
47 VO_QUEUE,
48 VI_QUEUE,
49 BE_QUEUE,
50 BK_QUEUE
51 };
52
_rtl_mac_to_hwqueue(struct ieee80211_hw * hw,struct sk_buff * skb)53 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
54 struct sk_buff *skb)
55 {
56 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
57 __le16 fc = rtl_get_fc(skb);
58 u8 queue_index = skb_get_queue_mapping(skb);
59
60 if (unlikely(ieee80211_is_beacon(fc)))
61 return BEACON_QUEUE;
62 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
63 return MGNT_QUEUE;
64 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
65 if (ieee80211_is_nullfunc(fc))
66 return HIGH_QUEUE;
67
68 return ac_to_hwq[queue_index];
69 }
70
71 /* Update PCI dependent default settings*/
_rtl_pci_update_default_setting(struct ieee80211_hw * hw)72 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
73 {
74 struct rtl_priv *rtlpriv = rtl_priv(hw);
75 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
76 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
77 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
78 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
79 u8 init_aspm;
80
81 ppsc->reg_rfps_level = 0;
82 ppsc->support_aspm = false;
83
84 /*Update PCI ASPM setting */
85 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
86 switch (rtlpci->const_pci_aspm) {
87 case 0:
88 /*No ASPM */
89 break;
90
91 case 1:
92 /*ASPM dynamically enabled/disable. */
93 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
94 break;
95
96 case 2:
97 /*ASPM with Clock Req dynamically enabled/disable. */
98 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
99 RT_RF_OFF_LEVL_CLK_REQ);
100 break;
101
102 case 3:
103 /*
104 * Always enable ASPM and Clock Req
105 * from initialization to halt.
106 * */
107 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
108 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
109 RT_RF_OFF_LEVL_CLK_REQ);
110 break;
111
112 case 4:
113 /*
114 * Always enable ASPM without Clock Req
115 * from initialization to halt.
116 * */
117 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
118 RT_RF_OFF_LEVL_CLK_REQ);
119 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
120 break;
121 }
122
123 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
124
125 /*Update Radio OFF setting */
126 switch (rtlpci->const_hwsw_rfoff_d3) {
127 case 1:
128 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
129 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
130 break;
131
132 case 2:
133 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
134 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
135 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
136 break;
137
138 case 3:
139 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
140 break;
141 }
142
143 /*Set HW definition to determine if it supports ASPM. */
144 switch (rtlpci->const_support_pciaspm) {
145 case 0:{
146 /*Not support ASPM. */
147 bool support_aspm = false;
148 ppsc->support_aspm = support_aspm;
149 break;
150 }
151 case 1:{
152 /*Support ASPM. */
153 bool support_aspm = true;
154 bool support_backdoor = true;
155 ppsc->support_aspm = support_aspm;
156
157 /*if (priv->oem_id == RT_CID_TOSHIBA &&
158 !priv->ndis_adapter.amd_l1_patch)
159 support_backdoor = false; */
160
161 ppsc->support_backdoor = support_backdoor;
162
163 break;
164 }
165 case 2:
166 /*ASPM value set by chipset. */
167 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
168 bool support_aspm = true;
169 ppsc->support_aspm = support_aspm;
170 }
171 break;
172 default:
173 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
174 "switch case not processed\n");
175 break;
176 }
177
178 /* toshiba aspm issue, toshiba will set aspm selfly
179 * so we should not set aspm in driver */
180 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
181 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
182 init_aspm == 0x43)
183 ppsc->support_aspm = false;
184 }
185
_rtl_pci_platform_switch_device_pci_aspm(struct ieee80211_hw * hw,u8 value)186 static bool _rtl_pci_platform_switch_device_pci_aspm(
187 struct ieee80211_hw *hw,
188 u8 value)
189 {
190 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
191 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
192
193 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
194 value |= 0x40;
195
196 pci_write_config_byte(rtlpci->pdev, 0x80, value);
197
198 return false;
199 }
200
201 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
_rtl_pci_switch_clk_req(struct ieee80211_hw * hw,u8 value)202 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
203 {
204 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
205 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
206
207 pci_write_config_byte(rtlpci->pdev, 0x81, value);
208
209 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
210 udelay(100);
211 }
212
213 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
rtl_pci_disable_aspm(struct ieee80211_hw * hw)214 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
215 {
216 struct rtl_priv *rtlpriv = rtl_priv(hw);
217 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
218 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
219 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
220 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
221 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
222 /*Retrieve original configuration settings. */
223 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
224 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
225 pcibridge_linkctrlreg;
226 u16 aspmlevel = 0;
227 u8 tmp_u1b = 0;
228
229 if (!ppsc->support_aspm)
230 return;
231
232 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
233 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
234 "PCI(Bridge) UNKNOWN\n");
235
236 return;
237 }
238
239 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
240 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
241 _rtl_pci_switch_clk_req(hw, 0x0);
242 }
243
244 /*for promising device will in L0 state after an I/O. */
245 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
246
247 /*Set corresponding value. */
248 aspmlevel |= BIT(0) | BIT(1);
249 linkctrl_reg &= ~aspmlevel;
250 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
251
252 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
253 udelay(50);
254
255 /*4 Disable Pci Bridge ASPM */
256 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
257 pcibridge_linkctrlreg);
258
259 udelay(50);
260 }
261
262 /*
263 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
264 *power saving We should follow the sequence to enable
265 *RTL8192SE first then enable Pci Bridge ASPM
266 *or the system will show bluescreen.
267 */
rtl_pci_enable_aspm(struct ieee80211_hw * hw)268 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
269 {
270 struct rtl_priv *rtlpriv = rtl_priv(hw);
271 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
272 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
273 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
274 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
275 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
276 u16 aspmlevel;
277 u8 u_pcibridge_aspmsetting;
278 u8 u_device_aspmsetting;
279
280 if (!ppsc->support_aspm)
281 return;
282
283 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
284 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
285 "PCI(Bridge) UNKNOWN\n");
286 return;
287 }
288
289 /*4 Enable Pci Bridge ASPM */
290
291 u_pcibridge_aspmsetting =
292 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
293 rtlpci->const_hostpci_aspm_setting;
294
295 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
296 u_pcibridge_aspmsetting &= ~BIT(0);
297
298 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
299 u_pcibridge_aspmsetting);
300
301 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
302 "PlatformEnableASPM(): Write reg[%x] = %x\n",
303 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
304 u_pcibridge_aspmsetting);
305
306 udelay(50);
307
308 /*Get ASPM level (with/without Clock Req) */
309 aspmlevel = rtlpci->const_devicepci_aspm_setting;
310 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
311
312 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
313 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
314
315 u_device_aspmsetting |= aspmlevel;
316
317 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
318
319 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
320 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
321 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
322 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
323 }
324 udelay(100);
325 }
326
rtl_pci_get_amd_l1_patch(struct ieee80211_hw * hw)327 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
328 {
329 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
330
331 bool status = false;
332 u8 offset_e0;
333 unsigned offset_e4;
334
335 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
336
337 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
338
339 if (offset_e0 == 0xA0) {
340 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
341 if (offset_e4 & BIT(23))
342 status = true;
343 }
344
345 return status;
346 }
347
rtl_pci_check_buddy_priv(struct ieee80211_hw * hw,struct rtl_priv ** buddy_priv)348 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
349 struct rtl_priv **buddy_priv)
350 {
351 struct rtl_priv *rtlpriv = rtl_priv(hw);
352 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
353 bool find_buddy_priv = false;
354 struct rtl_priv *tpriv = NULL;
355 struct rtl_pci_priv *tpcipriv = NULL;
356
357 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
358 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
359 list) {
360 if (tpriv) {
361 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
362 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
363 "pcipriv->ndis_adapter.funcnumber %x\n",
364 pcipriv->ndis_adapter.funcnumber);
365 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
366 "tpcipriv->ndis_adapter.funcnumber %x\n",
367 tpcipriv->ndis_adapter.funcnumber);
368
369 if ((pcipriv->ndis_adapter.busnumber ==
370 tpcipriv->ndis_adapter.busnumber) &&
371 (pcipriv->ndis_adapter.devnumber ==
372 tpcipriv->ndis_adapter.devnumber) &&
373 (pcipriv->ndis_adapter.funcnumber !=
374 tpcipriv->ndis_adapter.funcnumber)) {
375 find_buddy_priv = true;
376 break;
377 }
378 }
379 }
380 }
381
382 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
383 "find_buddy_priv %d\n", find_buddy_priv);
384
385 if (find_buddy_priv)
386 *buddy_priv = tpriv;
387
388 return find_buddy_priv;
389 }
390
rtl_pci_get_linkcontrol_field(struct ieee80211_hw * hw)391 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
392 {
393 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
394 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
395 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
396 u8 linkctrl_reg;
397 u8 num4bbytes;
398
399 num4bbytes = (capabilityoffset + 0x10) / 4;
400
401 /*Read Link Control Register */
402 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
403
404 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
405 }
406
rtl_pci_parse_configuration(struct pci_dev * pdev,struct ieee80211_hw * hw)407 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
408 struct ieee80211_hw *hw)
409 {
410 struct rtl_priv *rtlpriv = rtl_priv(hw);
411 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
412
413 u8 tmp;
414 u16 linkctrl_reg;
415
416 /*Link Control Register */
417 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
418 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
419
420 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
421 pcipriv->ndis_adapter.linkctrl_reg);
422
423 pci_read_config_byte(pdev, 0x98, &tmp);
424 tmp |= BIT(4);
425 pci_write_config_byte(pdev, 0x98, tmp);
426
427 tmp = 0x17;
428 pci_write_config_byte(pdev, 0x70f, tmp);
429 }
430
rtl_pci_init_aspm(struct ieee80211_hw * hw)431 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
432 {
433 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
434
435 _rtl_pci_update_default_setting(hw);
436
437 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
438 /*Always enable ASPM & Clock Req. */
439 rtl_pci_enable_aspm(hw);
440 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
441 }
442
443 }
444
_rtl_pci_io_handler_init(struct device * dev,struct ieee80211_hw * hw)445 static void _rtl_pci_io_handler_init(struct device *dev,
446 struct ieee80211_hw *hw)
447 {
448 struct rtl_priv *rtlpriv = rtl_priv(hw);
449
450 rtlpriv->io.dev = dev;
451
452 rtlpriv->io.write8_async = pci_write8_async;
453 rtlpriv->io.write16_async = pci_write16_async;
454 rtlpriv->io.write32_async = pci_write32_async;
455
456 rtlpriv->io.read8_sync = pci_read8_sync;
457 rtlpriv->io.read16_sync = pci_read16_sync;
458 rtlpriv->io.read32_sync = pci_read32_sync;
459
460 }
461
_rtl_update_earlymode_info(struct ieee80211_hw * hw,struct sk_buff * skb,struct rtl_tcb_desc * tcb_desc,u8 tid)462 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
463 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
464 {
465 struct rtl_priv *rtlpriv = rtl_priv(hw);
466 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
467 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
468 struct sk_buff *next_skb;
469 u8 additionlen = FCS_LEN;
470
471 /* here open is 4, wep/tkip is 8, aes is 12*/
472 if (info->control.hw_key)
473 additionlen += info->control.hw_key->icv_len;
474
475 /* The most skb num is 6 */
476 tcb_desc->empkt_num = 0;
477 spin_lock_bh(&rtlpriv->locks.waitq_lock);
478 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
479 struct ieee80211_tx_info *next_info;
480
481 next_info = IEEE80211_SKB_CB(next_skb);
482 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
483 tcb_desc->empkt_len[tcb_desc->empkt_num] =
484 next_skb->len + additionlen;
485 tcb_desc->empkt_num++;
486 } else {
487 break;
488 }
489
490 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
491 next_skb))
492 break;
493
494 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
495 break;
496 }
497 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
498
499 return true;
500 }
501
502 /* just for early mode now */
_rtl_pci_tx_chk_waitq(struct ieee80211_hw * hw)503 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
504 {
505 struct rtl_priv *rtlpriv = rtl_priv(hw);
506 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
507 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
508 struct sk_buff *skb = NULL;
509 struct ieee80211_tx_info *info = NULL;
510 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
511 int tid;
512
513 if (!rtlpriv->rtlhal.earlymode_enable)
514 return;
515
516 if (rtlpriv->dm.supp_phymode_switch &&
517 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
518 (rtlpriv->buddy_priv &&
519 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
520 return;
521 /* we juse use em for BE/BK/VI/VO */
522 for (tid = 7; tid >= 0; tid--) {
523 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
524 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
525 while (!mac->act_scanning &&
526 rtlpriv->psc.rfpwr_state == ERFON) {
527 struct rtl_tcb_desc tcb_desc;
528 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
529
530 spin_lock_bh(&rtlpriv->locks.waitq_lock);
531 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
532 (ring->entries - skb_queue_len(&ring->queue) >
533 rtlhal->max_earlymode_num)) {
534 skb = skb_dequeue(&mac->skb_waitq[tid]);
535 } else {
536 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
537 break;
538 }
539 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
540
541 /* Some macaddr can't do early mode. like
542 * multicast/broadcast/no_qos data */
543 info = IEEE80211_SKB_CB(skb);
544 if (info->flags & IEEE80211_TX_CTL_AMPDU)
545 _rtl_update_earlymode_info(hw, skb,
546 &tcb_desc, tid);
547
548 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
549 }
550 }
551 }
552
553
_rtl_pci_tx_isr(struct ieee80211_hw * hw,int prio)554 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
555 {
556 struct rtl_priv *rtlpriv = rtl_priv(hw);
557 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
558
559 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
560
561 while (skb_queue_len(&ring->queue)) {
562 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
563 struct sk_buff *skb;
564 struct ieee80211_tx_info *info;
565 __le16 fc;
566 u8 tid;
567
568 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
569 HW_DESC_OWN);
570
571 /*beacon packet will only use the first
572 *descriptor by defaut, and the own may not
573 *be cleared by the hardware
574 */
575 if (own)
576 return;
577 ring->idx = (ring->idx + 1) % ring->entries;
578
579 skb = __skb_dequeue(&ring->queue);
580 pci_unmap_single(rtlpci->pdev,
581 rtlpriv->cfg->ops->
582 get_desc((u8 *) entry, true,
583 HW_DESC_TXBUFF_ADDR),
584 skb->len, PCI_DMA_TODEVICE);
585
586 /* remove early mode header */
587 if (rtlpriv->rtlhal.earlymode_enable)
588 skb_pull(skb, EM_HDR_LEN);
589
590 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
591 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
592 ring->idx,
593 skb_queue_len(&ring->queue),
594 *(u16 *) (skb->data + 22));
595
596 if (prio == TXCMD_QUEUE) {
597 dev_kfree_skb(skb);
598 goto tx_status_ok;
599
600 }
601
602 /* for sw LPS, just after NULL skb send out, we can
603 * sure AP knows we are sleeping, we should not let
604 * rf sleep
605 */
606 fc = rtl_get_fc(skb);
607 if (ieee80211_is_nullfunc(fc)) {
608 if (ieee80211_has_pm(fc)) {
609 rtlpriv->mac80211.offchan_delay = true;
610 rtlpriv->psc.state_inap = true;
611 } else {
612 rtlpriv->psc.state_inap = false;
613 }
614 }
615 if (ieee80211_is_action(fc)) {
616 struct ieee80211_mgmt *action_frame =
617 (struct ieee80211_mgmt *)skb->data;
618 if (action_frame->u.action.u.ht_smps.action ==
619 WLAN_HT_ACTION_SMPS) {
620 dev_kfree_skb(skb);
621 goto tx_status_ok;
622 }
623 }
624
625 /* update tid tx pkt num */
626 tid = rtl_get_tid(skb);
627 if (tid <= 7)
628 rtlpriv->link_info.tidtx_inperiod[tid]++;
629
630 info = IEEE80211_SKB_CB(skb);
631 ieee80211_tx_info_clear_status(info);
632
633 info->flags |= IEEE80211_TX_STAT_ACK;
634 /*info->status.rates[0].count = 1; */
635
636 ieee80211_tx_status_irqsafe(hw, skb);
637
638 if ((ring->entries - skb_queue_len(&ring->queue))
639 == 2) {
640
641 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
642 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%d\n",
643 prio, ring->idx,
644 skb_queue_len(&ring->queue));
645
646 ieee80211_wake_queue(hw,
647 skb_get_queue_mapping
648 (skb));
649 }
650 tx_status_ok:
651 skb = NULL;
652 }
653
654 if (((rtlpriv->link_info.num_rx_inperiod +
655 rtlpriv->link_info.num_tx_inperiod) > 8) ||
656 (rtlpriv->link_info.num_rx_inperiod > 2)) {
657 rtlpriv->enter_ps = false;
658 schedule_work(&rtlpriv->works.lps_change_work);
659 }
660 }
661
_rtl_receive_one(struct ieee80211_hw * hw,struct sk_buff * skb,struct ieee80211_rx_status rx_status)662 static void _rtl_receive_one(struct ieee80211_hw *hw, struct sk_buff *skb,
663 struct ieee80211_rx_status rx_status)
664 {
665 struct rtl_priv *rtlpriv = rtl_priv(hw);
666 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
667 __le16 fc = rtl_get_fc(skb);
668 bool unicast = false;
669 struct sk_buff *uskb = NULL;
670 u8 *pdata;
671
672
673 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
674
675 if (is_broadcast_ether_addr(hdr->addr1)) {
676 ;/*TODO*/
677 } else if (is_multicast_ether_addr(hdr->addr1)) {
678 ;/*TODO*/
679 } else {
680 unicast = true;
681 rtlpriv->stats.rxbytesunicast += skb->len;
682 }
683
684 rtl_is_special_data(hw, skb, false);
685
686 if (ieee80211_is_data(fc)) {
687 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
688
689 if (unicast)
690 rtlpriv->link_info.num_rx_inperiod++;
691 }
692
693 /* static bcn for roaming */
694 rtl_beacon_statistic(hw, skb);
695 rtl_p2p_info(hw, (void *)skb->data, skb->len);
696
697 /* for sw lps */
698 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
699 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
700 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
701 (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) &&
702 (ieee80211_is_beacon(fc) || ieee80211_is_probe_resp(fc)))
703 return;
704
705 if (unlikely(!rtl_action_proc(hw, skb, false)))
706 return;
707
708 uskb = dev_alloc_skb(skb->len + 128);
709 if (!uskb)
710 return; /* exit if allocation failed */
711 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, sizeof(rx_status));
712 pdata = (u8 *)skb_put(uskb, skb->len);
713 memcpy(pdata, skb->data, skb->len);
714
715 ieee80211_rx_irqsafe(hw, uskb);
716 }
717
_rtl_pci_rx_interrupt(struct ieee80211_hw * hw)718 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
719 {
720 struct rtl_priv *rtlpriv = rtl_priv(hw);
721 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
722 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
723
724 struct ieee80211_rx_status rx_status = { 0 };
725 unsigned int count = rtlpci->rxringcount;
726 u8 own;
727 u8 tmp_one;
728 u32 bufferaddress;
729
730 struct rtl_stats stats = {
731 .signal = 0,
732 .noise = -98,
733 .rate = 0,
734 };
735 int index = rtlpci->rx_ring[rx_queue_idx].idx;
736
737 /*RX NORMAL PKT */
738 while (count--) {
739 /*rx descriptor */
740 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
741 index];
742 /*rx pkt */
743 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
744 index];
745 struct sk_buff *new_skb = NULL;
746
747 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
748 false, HW_DESC_OWN);
749
750 /*wait data to be filled by hardware */
751 if (own)
752 break;
753
754 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
755 &rx_status,
756 (u8 *) pdesc, skb);
757
758 if (stats.crc || stats.hwerror)
759 goto done;
760
761 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
762 if (unlikely(!new_skb)) {
763 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV), DBG_DMESG,
764 "can't alloc skb for rx\n");
765 goto done;
766 }
767 kmemleak_not_leak(new_skb);
768
769 pci_unmap_single(rtlpci->pdev,
770 *((dma_addr_t *) skb->cb),
771 rtlpci->rxbuffersize,
772 PCI_DMA_FROMDEVICE);
773
774 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, false,
775 HW_DESC_RXPKT_LEN));
776 skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift);
777
778 /*
779 * NOTICE This can not be use for mac80211,
780 * this is done in mac80211 code,
781 * if you done here sec DHCP will fail
782 * skb_trim(skb, skb->len - 4);
783 */
784
785 _rtl_receive_one(hw, skb, rx_status);
786
787 if (((rtlpriv->link_info.num_rx_inperiod +
788 rtlpriv->link_info.num_tx_inperiod) > 8) ||
789 (rtlpriv->link_info.num_rx_inperiod > 2)) {
790 rtlpriv->enter_ps = false;
791 schedule_work(&rtlpriv->works.lps_change_work);
792 }
793
794 dev_kfree_skb_any(skb);
795 skb = new_skb;
796
797 rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
798 *((dma_addr_t *) skb->cb) =
799 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
800 rtlpci->rxbuffersize,
801 PCI_DMA_FROMDEVICE);
802
803 done:
804 bufferaddress = (*((dma_addr_t *)skb->cb));
805 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
806 return;
807 tmp_one = 1;
808 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
809 HW_DESC_RXBUFF_ADDR,
810 (u8 *)&bufferaddress);
811 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
812 HW_DESC_RXPKT_LEN,
813 (u8 *)&rtlpci->rxbuffersize);
814
815 if (index == rtlpci->rxringcount - 1)
816 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
817 HW_DESC_RXERO,
818 &tmp_one);
819
820 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
821 &tmp_one);
822
823 index = (index + 1) % rtlpci->rxringcount;
824 }
825
826 rtlpci->rx_ring[rx_queue_idx].idx = index;
827 }
828
_rtl_pci_interrupt(int irq,void * dev_id)829 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
830 {
831 struct ieee80211_hw *hw = dev_id;
832 struct rtl_priv *rtlpriv = rtl_priv(hw);
833 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
834 unsigned long flags;
835 u32 inta = 0;
836 u32 intb = 0;
837 irqreturn_t ret = IRQ_HANDLED;
838
839 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
840
841 /*read ISR: 4/8bytes */
842 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
843
844 /*Shared IRQ or HW disappared */
845 if (!inta || inta == 0xffff) {
846 ret = IRQ_NONE;
847 goto done;
848 }
849
850 /*<1> beacon related */
851 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
852 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
853 "beacon ok interrupt!\n");
854 }
855
856 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
857 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
858 "beacon err interrupt!\n");
859 }
860
861 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
862 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
863 }
864
865 if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
866 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
867 "prepare beacon for interrupt!\n");
868 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
869 }
870
871 /*<3> Tx related */
872 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
873 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
874
875 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
876 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
877 "Manage ok interrupt!\n");
878 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
879 }
880
881 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
882 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
883 "HIGH_QUEUE ok interrupt!\n");
884 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
885 }
886
887 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
888 rtlpriv->link_info.num_tx_inperiod++;
889
890 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
891 "BK Tx OK interrupt!\n");
892 _rtl_pci_tx_isr(hw, BK_QUEUE);
893 }
894
895 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
896 rtlpriv->link_info.num_tx_inperiod++;
897
898 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
899 "BE TX OK interrupt!\n");
900 _rtl_pci_tx_isr(hw, BE_QUEUE);
901 }
902
903 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
904 rtlpriv->link_info.num_tx_inperiod++;
905
906 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
907 "VI TX OK interrupt!\n");
908 _rtl_pci_tx_isr(hw, VI_QUEUE);
909 }
910
911 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
912 rtlpriv->link_info.num_tx_inperiod++;
913
914 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
915 "Vo TX OK interrupt!\n");
916 _rtl_pci_tx_isr(hw, VO_QUEUE);
917 }
918
919 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
920 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
921 rtlpriv->link_info.num_tx_inperiod++;
922
923 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
924 "CMD TX OK interrupt!\n");
925 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
926 }
927 }
928
929 /*<2> Rx related */
930 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
931 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
932 _rtl_pci_rx_interrupt(hw);
933 }
934
935 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
936 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
937 "rx descriptor unavailable!\n");
938 _rtl_pci_rx_interrupt(hw);
939 }
940
941 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
942 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
943 _rtl_pci_rx_interrupt(hw);
944 }
945
946 /*fw related*/
947 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
948 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
949 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
950 "firmware interrupt!\n");
951 queue_delayed_work(rtlpriv->works.rtl_wq,
952 &rtlpriv->works.fwevt_wq, 0);
953 }
954 }
955
956 if (rtlpriv->rtlhal.earlymode_enable)
957 tasklet_schedule(&rtlpriv->works.irq_tasklet);
958
959 done:
960 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
961 return ret;
962 }
963
_rtl_pci_irq_tasklet(struct ieee80211_hw * hw)964 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
965 {
966 _rtl_pci_tx_chk_waitq(hw);
967 }
968
_rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw * hw)969 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
970 {
971 struct rtl_priv *rtlpriv = rtl_priv(hw);
972 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
973 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
974 struct rtl8192_tx_ring *ring = NULL;
975 struct ieee80211_hdr *hdr = NULL;
976 struct ieee80211_tx_info *info = NULL;
977 struct sk_buff *pskb = NULL;
978 struct rtl_tx_desc *pdesc = NULL;
979 struct rtl_tcb_desc tcb_desc;
980 u8 temp_one = 1;
981
982 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
983 ring = &rtlpci->tx_ring[BEACON_QUEUE];
984 pskb = __skb_dequeue(&ring->queue);
985 if (pskb) {
986 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
987 pci_unmap_single(rtlpci->pdev, rtlpriv->cfg->ops->get_desc(
988 (u8 *) entry, true, HW_DESC_TXBUFF_ADDR),
989 pskb->len, PCI_DMA_TODEVICE);
990 kfree_skb(pskb);
991 }
992
993 /*NB: the beacon data buffer must be 32-bit aligned. */
994 pskb = ieee80211_beacon_get(hw, mac->vif);
995 if (pskb == NULL)
996 return;
997 hdr = rtl_get_hdr(pskb);
998 info = IEEE80211_SKB_CB(pskb);
999 pdesc = &ring->desc[0];
1000 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
1001 info, NULL, pskb, BEACON_QUEUE, &tcb_desc);
1002
1003 __skb_queue_tail(&ring->queue, pskb);
1004
1005 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
1006 &temp_one);
1007
1008 return;
1009 }
1010
rtl_lps_change_work_callback(struct work_struct * work)1011 static void rtl_lps_change_work_callback(struct work_struct *work)
1012 {
1013 struct rtl_works *rtlworks =
1014 container_of(work, struct rtl_works, lps_change_work);
1015 struct ieee80211_hw *hw = rtlworks->hw;
1016 struct rtl_priv *rtlpriv = rtl_priv(hw);
1017
1018 if (rtlpriv->enter_ps)
1019 rtl_lps_enter(hw);
1020 else
1021 rtl_lps_leave(hw);
1022 }
1023
_rtl_pci_init_trx_var(struct ieee80211_hw * hw)1024 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1025 {
1026 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1027 u8 i;
1028
1029 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1030 rtlpci->txringcount[i] = RT_TXDESC_NUM;
1031
1032 /*
1033 *we just alloc 2 desc for beacon queue,
1034 *because we just need first desc in hw beacon.
1035 */
1036 rtlpci->txringcount[BEACON_QUEUE] = 2;
1037
1038 /*
1039 *BE queue need more descriptor for performance
1040 *consideration or, No more tx desc will happen,
1041 *and may cause mac80211 mem leakage.
1042 */
1043 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1044
1045 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1046 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1047 }
1048
_rtl_pci_init_struct(struct ieee80211_hw * hw,struct pci_dev * pdev)1049 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1050 struct pci_dev *pdev)
1051 {
1052 struct rtl_priv *rtlpriv = rtl_priv(hw);
1053 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1054 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1055 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1056
1057 rtlpci->up_first_time = true;
1058 rtlpci->being_init_adapter = false;
1059
1060 rtlhal->hw = hw;
1061 rtlpci->pdev = pdev;
1062
1063 /*Tx/Rx related var */
1064 _rtl_pci_init_trx_var(hw);
1065
1066 /*IBSS*/ mac->beacon_interval = 100;
1067
1068 /*AMPDU*/
1069 mac->min_space_cfg = 0;
1070 mac->max_mss_density = 0;
1071 /*set sane AMPDU defaults */
1072 mac->current_ampdu_density = 7;
1073 mac->current_ampdu_factor = 3;
1074
1075 /*QOS*/
1076 rtlpci->acm_method = eAcmWay2_SW;
1077
1078 /*task */
1079 tasklet_init(&rtlpriv->works.irq_tasklet,
1080 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1081 (unsigned long)hw);
1082 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1083 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1084 (unsigned long)hw);
1085 INIT_WORK(&rtlpriv->works.lps_change_work,
1086 rtl_lps_change_work_callback);
1087 }
1088
_rtl_pci_init_tx_ring(struct ieee80211_hw * hw,unsigned int prio,unsigned int entries)1089 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1090 unsigned int prio, unsigned int entries)
1091 {
1092 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1093 struct rtl_priv *rtlpriv = rtl_priv(hw);
1094 struct rtl_tx_desc *ring;
1095 dma_addr_t dma;
1096 u32 nextdescaddress;
1097 int i;
1098
1099 ring = pci_alloc_consistent(rtlpci->pdev,
1100 sizeof(*ring) * entries, &dma);
1101
1102 if (!ring || (unsigned long)ring & 0xFF) {
1103 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1104 "Cannot allocate TX ring (prio = %d)\n", prio);
1105 return -ENOMEM;
1106 }
1107
1108 memset(ring, 0, sizeof(*ring) * entries);
1109 rtlpci->tx_ring[prio].desc = ring;
1110 rtlpci->tx_ring[prio].dma = dma;
1111 rtlpci->tx_ring[prio].idx = 0;
1112 rtlpci->tx_ring[prio].entries = entries;
1113 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1114
1115 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1116 prio, ring);
1117
1118 for (i = 0; i < entries; i++) {
1119 nextdescaddress = (u32) dma +
1120 ((i + 1) % entries) *
1121 sizeof(*ring);
1122
1123 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1124 true, HW_DESC_TX_NEXTDESC_ADDR,
1125 (u8 *)&nextdescaddress);
1126 }
1127
1128 return 0;
1129 }
1130
_rtl_pci_init_rx_ring(struct ieee80211_hw * hw)1131 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1132 {
1133 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1134 struct rtl_priv *rtlpriv = rtl_priv(hw);
1135 struct rtl_rx_desc *entry = NULL;
1136 int i, rx_queue_idx;
1137 u8 tmp_one = 1;
1138
1139 /*
1140 *rx_queue_idx 0:RX_MPDU_QUEUE
1141 *rx_queue_idx 1:RX_CMD_QUEUE
1142 */
1143 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1144 rx_queue_idx++) {
1145 rtlpci->rx_ring[rx_queue_idx].desc =
1146 pci_alloc_consistent(rtlpci->pdev,
1147 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1148 desc) * rtlpci->rxringcount,
1149 &rtlpci->rx_ring[rx_queue_idx].dma);
1150
1151 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1152 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1153 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1154 "Cannot allocate RX ring\n");
1155 return -ENOMEM;
1156 }
1157
1158 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1159 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1160 rtlpci->rxringcount);
1161
1162 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1163
1164 /* If amsdu_8k is disabled, set buffersize to 4096. This
1165 * change will reduce memory fragmentation.
1166 */
1167 if (rtlpci->rxbuffersize > 4096 &&
1168 rtlpriv->rtlhal.disable_amsdu_8k)
1169 rtlpci->rxbuffersize = 4096;
1170
1171 for (i = 0; i < rtlpci->rxringcount; i++) {
1172 struct sk_buff *skb =
1173 dev_alloc_skb(rtlpci->rxbuffersize);
1174 u32 bufferaddress;
1175 if (!skb)
1176 return 0;
1177 kmemleak_not_leak(skb);
1178 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1179
1180 /*skb->dev = dev; */
1181
1182 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1183
1184 /*
1185 *just set skb->cb to mapping addr
1186 *for pci_unmap_single use
1187 */
1188 *((dma_addr_t *) skb->cb) =
1189 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1190 rtlpci->rxbuffersize,
1191 PCI_DMA_FROMDEVICE);
1192
1193 bufferaddress = (*((dma_addr_t *)skb->cb));
1194 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress)) {
1195 dev_kfree_skb_any(skb);
1196 return 1;
1197 }
1198 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1199 HW_DESC_RXBUFF_ADDR,
1200 (u8 *)&bufferaddress);
1201 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1202 HW_DESC_RXPKT_LEN,
1203 (u8 *)&rtlpci->
1204 rxbuffersize);
1205 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1206 HW_DESC_RXOWN,
1207 &tmp_one);
1208 }
1209
1210 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1211 HW_DESC_RXERO, &tmp_one);
1212 }
1213 return 0;
1214 }
1215
_rtl_pci_free_tx_ring(struct ieee80211_hw * hw,unsigned int prio)1216 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1217 unsigned int prio)
1218 {
1219 struct rtl_priv *rtlpriv = rtl_priv(hw);
1220 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1221 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1222
1223 while (skb_queue_len(&ring->queue)) {
1224 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1225 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1226
1227 pci_unmap_single(rtlpci->pdev,
1228 rtlpriv->cfg->
1229 ops->get_desc((u8 *) entry, true,
1230 HW_DESC_TXBUFF_ADDR),
1231 skb->len, PCI_DMA_TODEVICE);
1232 kfree_skb(skb);
1233 ring->idx = (ring->idx + 1) % ring->entries;
1234 }
1235
1236 if (ring->desc) {
1237 pci_free_consistent(rtlpci->pdev,
1238 sizeof(*ring->desc) * ring->entries,
1239 ring->desc, ring->dma);
1240 ring->desc = NULL;
1241 }
1242 }
1243
_rtl_pci_free_rx_ring(struct rtl_pci * rtlpci)1244 static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1245 {
1246 int i, rx_queue_idx;
1247
1248 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1249 /*rx_queue_idx 1:RX_CMD_QUEUE */
1250 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1251 rx_queue_idx++) {
1252 for (i = 0; i < rtlpci->rxringcount; i++) {
1253 struct sk_buff *skb =
1254 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1255 if (!skb)
1256 continue;
1257
1258 pci_unmap_single(rtlpci->pdev,
1259 *((dma_addr_t *) skb->cb),
1260 rtlpci->rxbuffersize,
1261 PCI_DMA_FROMDEVICE);
1262 kfree_skb(skb);
1263 }
1264
1265 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1266 pci_free_consistent(rtlpci->pdev,
1267 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1268 desc) * rtlpci->rxringcount,
1269 rtlpci->rx_ring[rx_queue_idx].desc,
1270 rtlpci->rx_ring[rx_queue_idx].dma);
1271 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1272 }
1273 }
1274 }
1275
_rtl_pci_init_trx_ring(struct ieee80211_hw * hw)1276 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1277 {
1278 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1279 int ret;
1280 int i;
1281
1282 ret = _rtl_pci_init_rx_ring(hw);
1283 if (ret)
1284 return ret;
1285
1286 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1287 ret = _rtl_pci_init_tx_ring(hw, i,
1288 rtlpci->txringcount[i]);
1289 if (ret)
1290 goto err_free_rings;
1291 }
1292
1293 return 0;
1294
1295 err_free_rings:
1296 _rtl_pci_free_rx_ring(rtlpci);
1297
1298 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1299 if (rtlpci->tx_ring[i].desc)
1300 _rtl_pci_free_tx_ring(hw, i);
1301
1302 return 1;
1303 }
1304
_rtl_pci_deinit_trx_ring(struct ieee80211_hw * hw)1305 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1306 {
1307 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1308 u32 i;
1309
1310 /*free rx rings */
1311 _rtl_pci_free_rx_ring(rtlpci);
1312
1313 /*free tx rings */
1314 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1315 _rtl_pci_free_tx_ring(hw, i);
1316
1317 return 0;
1318 }
1319
rtl_pci_reset_trx_ring(struct ieee80211_hw * hw)1320 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1321 {
1322 struct rtl_priv *rtlpriv = rtl_priv(hw);
1323 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1324 int i, rx_queue_idx;
1325 unsigned long flags;
1326 u8 tmp_one = 1;
1327
1328 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1329 /*rx_queue_idx 1:RX_CMD_QUEUE */
1330 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1331 rx_queue_idx++) {
1332 /*
1333 *force the rx_ring[RX_MPDU_QUEUE/
1334 *RX_CMD_QUEUE].idx to the first one
1335 */
1336 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1337 struct rtl_rx_desc *entry = NULL;
1338
1339 for (i = 0; i < rtlpci->rxringcount; i++) {
1340 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1341 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1342 false,
1343 HW_DESC_RXOWN,
1344 &tmp_one);
1345 }
1346 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1347 }
1348 }
1349
1350 /*
1351 *after reset, release previous pending packet,
1352 *and force the tx idx to the first one
1353 */
1354 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1355 if (rtlpci->tx_ring[i].desc) {
1356 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1357
1358 while (skb_queue_len(&ring->queue)) {
1359 struct rtl_tx_desc *entry;
1360 struct sk_buff *skb;
1361
1362 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock,
1363 flags);
1364 entry = &ring->desc[ring->idx];
1365 skb = __skb_dequeue(&ring->queue);
1366 pci_unmap_single(rtlpci->pdev,
1367 rtlpriv->cfg->ops->
1368 get_desc((u8 *)
1369 entry,
1370 true,
1371 HW_DESC_TXBUFF_ADDR),
1372 skb->len, PCI_DMA_TODEVICE);
1373 ring->idx = (ring->idx + 1) % ring->entries;
1374 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1375 flags);
1376 kfree_skb(skb);
1377 }
1378 ring->idx = 0;
1379 }
1380 }
1381
1382 return 0;
1383 }
1384
rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb)1385 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1386 struct ieee80211_sta *sta,
1387 struct sk_buff *skb)
1388 {
1389 struct rtl_priv *rtlpriv = rtl_priv(hw);
1390 struct rtl_sta_info *sta_entry = NULL;
1391 u8 tid = rtl_get_tid(skb);
1392 __le16 fc = rtl_get_fc(skb);
1393
1394 if (!sta)
1395 return false;
1396 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1397
1398 if (!rtlpriv->rtlhal.earlymode_enable)
1399 return false;
1400 if (ieee80211_is_nullfunc(fc))
1401 return false;
1402 if (ieee80211_is_qos_nullfunc(fc))
1403 return false;
1404 if (ieee80211_is_pspoll(fc))
1405 return false;
1406 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1407 return false;
1408 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1409 return false;
1410 if (tid > 7)
1411 return false;
1412
1413 /* maybe every tid should be checked */
1414 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1415 return false;
1416
1417 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1418 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1419 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1420
1421 return true;
1422 }
1423
rtl_pci_tx(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb,struct rtl_tcb_desc * ptcb_desc)1424 static int rtl_pci_tx(struct ieee80211_hw *hw,
1425 struct ieee80211_sta *sta,
1426 struct sk_buff *skb,
1427 struct rtl_tcb_desc *ptcb_desc)
1428 {
1429 struct rtl_priv *rtlpriv = rtl_priv(hw);
1430 struct rtl_sta_info *sta_entry = NULL;
1431 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1432 struct rtl8192_tx_ring *ring;
1433 struct rtl_tx_desc *pdesc;
1434 u8 idx;
1435 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1436 unsigned long flags;
1437 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1438 __le16 fc = rtl_get_fc(skb);
1439 u8 *pda_addr = hdr->addr1;
1440 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1441 /*ssn */
1442 u8 tid = 0;
1443 u16 seq_number = 0;
1444 u8 own;
1445 u8 temp_one = 1;
1446
1447 if (ieee80211_is_mgmt(fc))
1448 rtl_tx_mgmt_proc(hw, skb);
1449
1450 if (rtlpriv->psc.sw_ps_enabled) {
1451 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1452 !ieee80211_has_pm(fc))
1453 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1454 }
1455
1456 rtl_action_proc(hw, skb, true);
1457
1458 if (is_multicast_ether_addr(pda_addr))
1459 rtlpriv->stats.txbytesmulticast += skb->len;
1460 else if (is_broadcast_ether_addr(pda_addr))
1461 rtlpriv->stats.txbytesbroadcast += skb->len;
1462 else
1463 rtlpriv->stats.txbytesunicast += skb->len;
1464
1465 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1466 ring = &rtlpci->tx_ring[hw_queue];
1467 if (hw_queue != BEACON_QUEUE)
1468 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1469 ring->entries;
1470 else
1471 idx = 0;
1472
1473 pdesc = &ring->desc[idx];
1474 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1475 true, HW_DESC_OWN);
1476
1477 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1478 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1479 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1480 hw_queue, ring->idx, idx,
1481 skb_queue_len(&ring->queue));
1482
1483 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1484 return skb->len;
1485 }
1486
1487 if (ieee80211_is_data_qos(fc)) {
1488 tid = rtl_get_tid(skb);
1489 if (sta) {
1490 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1491 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1492 IEEE80211_SCTL_SEQ) >> 4;
1493 seq_number += 1;
1494
1495 if (!ieee80211_has_morefrags(hdr->frame_control))
1496 sta_entry->tids[tid].seq_number = seq_number;
1497 }
1498 }
1499
1500 if (ieee80211_is_data(fc))
1501 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1502
1503 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1504 info, sta, skb, hw_queue, ptcb_desc);
1505
1506 __skb_queue_tail(&ring->queue, skb);
1507
1508 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
1509 HW_DESC_OWN, &temp_one);
1510
1511
1512 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1513 hw_queue != BEACON_QUEUE) {
1514
1515 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1516 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1517 hw_queue, ring->idx, idx,
1518 skb_queue_len(&ring->queue));
1519
1520 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1521 }
1522
1523 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1524
1525 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1526
1527 return 0;
1528 }
1529
rtl_pci_flush(struct ieee80211_hw * hw,bool drop)1530 static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1531 {
1532 struct rtl_priv *rtlpriv = rtl_priv(hw);
1533 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1534 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1535 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1536 u16 i = 0;
1537 int queue_id;
1538 struct rtl8192_tx_ring *ring;
1539
1540 if (mac->skip_scan)
1541 return;
1542
1543 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1544 u32 queue_len;
1545 ring = &pcipriv->dev.tx_ring[queue_id];
1546 queue_len = skb_queue_len(&ring->queue);
1547 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1548 queue_id == TXCMD_QUEUE) {
1549 queue_id--;
1550 continue;
1551 } else {
1552 msleep(20);
1553 i++;
1554 }
1555
1556 /* we just wait 1s for all queues */
1557 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1558 is_hal_stop(rtlhal) || i >= 200)
1559 return;
1560 }
1561 }
1562
rtl_pci_deinit(struct ieee80211_hw * hw)1563 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1564 {
1565 struct rtl_priv *rtlpriv = rtl_priv(hw);
1566 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1567
1568 _rtl_pci_deinit_trx_ring(hw);
1569
1570 synchronize_irq(rtlpci->pdev->irq);
1571 tasklet_kill(&rtlpriv->works.irq_tasklet);
1572 cancel_work_sync(&rtlpriv->works.lps_change_work);
1573
1574 flush_workqueue(rtlpriv->works.rtl_wq);
1575 destroy_workqueue(rtlpriv->works.rtl_wq);
1576
1577 }
1578
rtl_pci_init(struct ieee80211_hw * hw,struct pci_dev * pdev)1579 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1580 {
1581 struct rtl_priv *rtlpriv = rtl_priv(hw);
1582 int err;
1583
1584 _rtl_pci_init_struct(hw, pdev);
1585
1586 err = _rtl_pci_init_trx_ring(hw);
1587 if (err) {
1588 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1589 "tx ring initialization failed\n");
1590 return err;
1591 }
1592
1593 return 0;
1594 }
1595
rtl_pci_start(struct ieee80211_hw * hw)1596 static int rtl_pci_start(struct ieee80211_hw *hw)
1597 {
1598 struct rtl_priv *rtlpriv = rtl_priv(hw);
1599 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1600 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1601 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1602
1603 int err;
1604
1605 rtl_pci_reset_trx_ring(hw);
1606
1607 rtlpci->driver_is_goingto_unload = false;
1608 err = rtlpriv->cfg->ops->hw_init(hw);
1609 if (err) {
1610 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1611 "Failed to config hardware!\n");
1612 return err;
1613 }
1614
1615 rtlpriv->cfg->ops->enable_interrupt(hw);
1616 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1617
1618 rtl_init_rx_config(hw);
1619
1620 /*should be after adapter start and interrupt enable. */
1621 set_hal_start(rtlhal);
1622
1623 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1624
1625 rtlpci->up_first_time = false;
1626
1627 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
1628 return 0;
1629 }
1630
rtl_pci_stop(struct ieee80211_hw * hw)1631 static void rtl_pci_stop(struct ieee80211_hw *hw)
1632 {
1633 struct rtl_priv *rtlpriv = rtl_priv(hw);
1634 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1635 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1636 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1637 unsigned long flags;
1638 u8 RFInProgressTimeOut = 0;
1639
1640 /*
1641 *should be before disable interrupt&adapter
1642 *and will do it immediately.
1643 */
1644 set_hal_stop(rtlhal);
1645
1646 rtlpriv->cfg->ops->disable_interrupt(hw);
1647 cancel_work_sync(&rtlpriv->works.lps_change_work);
1648
1649 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1650 while (ppsc->rfchange_inprogress) {
1651 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1652 if (RFInProgressTimeOut > 100) {
1653 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1654 break;
1655 }
1656 mdelay(1);
1657 RFInProgressTimeOut++;
1658 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1659 }
1660 ppsc->rfchange_inprogress = true;
1661 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1662
1663 rtlpci->driver_is_goingto_unload = true;
1664 rtlpriv->cfg->ops->hw_disable(hw);
1665 /* some things are not needed if firmware not available */
1666 if (!rtlpriv->max_fw_size)
1667 return;
1668 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1669
1670 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1671 ppsc->rfchange_inprogress = false;
1672 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1673
1674 rtl_pci_enable_aspm(hw);
1675 }
1676
_rtl_pci_find_adapter(struct pci_dev * pdev,struct ieee80211_hw * hw)1677 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1678 struct ieee80211_hw *hw)
1679 {
1680 struct rtl_priv *rtlpriv = rtl_priv(hw);
1681 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1682 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1683 struct pci_dev *bridge_pdev = pdev->bus->self;
1684 u16 venderid;
1685 u16 deviceid;
1686 u8 revisionid;
1687 u16 irqline;
1688 u8 tmp;
1689
1690 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1691 venderid = pdev->vendor;
1692 deviceid = pdev->device;
1693 pci_read_config_byte(pdev, 0x8, &revisionid);
1694 pci_read_config_word(pdev, 0x3C, &irqline);
1695
1696 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1697 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1698 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1699 * the correct driver is r8192e_pci, thus this routine should
1700 * return false.
1701 */
1702 if (deviceid == RTL_PCI_8192SE_DID &&
1703 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1704 return false;
1705
1706 if (deviceid == RTL_PCI_8192_DID ||
1707 deviceid == RTL_PCI_0044_DID ||
1708 deviceid == RTL_PCI_0047_DID ||
1709 deviceid == RTL_PCI_8192SE_DID ||
1710 deviceid == RTL_PCI_8174_DID ||
1711 deviceid == RTL_PCI_8173_DID ||
1712 deviceid == RTL_PCI_8172_DID ||
1713 deviceid == RTL_PCI_8171_DID) {
1714 switch (revisionid) {
1715 case RTL_PCI_REVISION_ID_8192PCIE:
1716 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1717 "8192 PCI-E is found - vid/did=%x/%x\n",
1718 venderid, deviceid);
1719 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1720 return false;
1721 case RTL_PCI_REVISION_ID_8192SE:
1722 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1723 "8192SE is found - vid/did=%x/%x\n",
1724 venderid, deviceid);
1725 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1726 break;
1727 default:
1728 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1729 "Err: Unknown device - vid/did=%x/%x\n",
1730 venderid, deviceid);
1731 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1732 break;
1733
1734 }
1735 } else if (deviceid == RTL_PCI_8723AE_DID) {
1736 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1737 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1738 "8723AE PCI-E is found - "
1739 "vid/did=%x/%x\n", venderid, deviceid);
1740 } else if (deviceid == RTL_PCI_8192CET_DID ||
1741 deviceid == RTL_PCI_8192CE_DID ||
1742 deviceid == RTL_PCI_8191CE_DID ||
1743 deviceid == RTL_PCI_8188CE_DID) {
1744 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1745 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1746 "8192C PCI-E is found - vid/did=%x/%x\n",
1747 venderid, deviceid);
1748 } else if (deviceid == RTL_PCI_8192DE_DID ||
1749 deviceid == RTL_PCI_8192DE_DID2) {
1750 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1751 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1752 "8192D PCI-E is found - vid/did=%x/%x\n",
1753 venderid, deviceid);
1754 } else if (deviceid == RTL_PCI_8188EE_DID) {
1755 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1756 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1757 "Find adapter, Hardware type is 8188EE\n");
1758 } else {
1759 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1760 "Err: Unknown device - vid/did=%x/%x\n",
1761 venderid, deviceid);
1762
1763 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1764 }
1765
1766 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1767 if (revisionid == 0 || revisionid == 1) {
1768 if (revisionid == 0) {
1769 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1770 "Find 92DE MAC0\n");
1771 rtlhal->interfaceindex = 0;
1772 } else if (revisionid == 1) {
1773 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1774 "Find 92DE MAC1\n");
1775 rtlhal->interfaceindex = 1;
1776 }
1777 } else {
1778 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1779 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1780 venderid, deviceid, revisionid);
1781 rtlhal->interfaceindex = 0;
1782 }
1783 }
1784 /*find bus info */
1785 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1786 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1787 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1788
1789 /* some ARM have no bridge_pdev and will crash here
1790 * so we should check if bridge_pdev is NULL
1791 */
1792 if (bridge_pdev) {
1793 /*find bridge info if available */
1794 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1795 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1796 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1797 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1798 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1799 "Pci Bridge Vendor is found index: %d\n",
1800 tmp);
1801 break;
1802 }
1803 }
1804 }
1805
1806 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1807 PCI_BRIDGE_VENDOR_UNKNOWN) {
1808 pcipriv->ndis_adapter.pcibridge_busnum =
1809 bridge_pdev->bus->number;
1810 pcipriv->ndis_adapter.pcibridge_devnum =
1811 PCI_SLOT(bridge_pdev->devfn);
1812 pcipriv->ndis_adapter.pcibridge_funcnum =
1813 PCI_FUNC(bridge_pdev->devfn);
1814 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1815 pci_pcie_cap(bridge_pdev);
1816 pcipriv->ndis_adapter.num4bytes =
1817 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1818
1819 rtl_pci_get_linkcontrol_field(hw);
1820
1821 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1822 PCI_BRIDGE_VENDOR_AMD) {
1823 pcipriv->ndis_adapter.amd_l1_patch =
1824 rtl_pci_get_amd_l1_patch(hw);
1825 }
1826 }
1827
1828 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1829 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
1830 pcipriv->ndis_adapter.busnumber,
1831 pcipriv->ndis_adapter.devnumber,
1832 pcipriv->ndis_adapter.funcnumber,
1833 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
1834
1835 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1836 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1837 pcipriv->ndis_adapter.pcibridge_busnum,
1838 pcipriv->ndis_adapter.pcibridge_devnum,
1839 pcipriv->ndis_adapter.pcibridge_funcnum,
1840 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1841 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1842 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1843 pcipriv->ndis_adapter.amd_l1_patch);
1844
1845 rtl_pci_parse_configuration(pdev, hw);
1846 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
1847
1848 return true;
1849 }
1850
rtl_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)1851 int rtl_pci_probe(struct pci_dev *pdev,
1852 const struct pci_device_id *id)
1853 {
1854 struct ieee80211_hw *hw = NULL;
1855
1856 struct rtl_priv *rtlpriv = NULL;
1857 struct rtl_pci_priv *pcipriv = NULL;
1858 struct rtl_pci *rtlpci;
1859 unsigned long pmem_start, pmem_len, pmem_flags;
1860 int err;
1861
1862 err = pci_enable_device(pdev);
1863 if (err) {
1864 RT_ASSERT(false, "%s : Cannot enable new PCI device\n",
1865 pci_name(pdev));
1866 return err;
1867 }
1868
1869 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1870 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1871 RT_ASSERT(false,
1872 "Unable to obtain 32bit DMA for consistent allocations\n");
1873 err = -ENOMEM;
1874 goto fail1;
1875 }
1876 }
1877
1878 pci_set_master(pdev);
1879
1880 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1881 sizeof(struct rtl_priv), &rtl_ops);
1882 if (!hw) {
1883 RT_ASSERT(false,
1884 "%s : ieee80211 alloc failed\n", pci_name(pdev));
1885 err = -ENOMEM;
1886 goto fail1;
1887 }
1888
1889 SET_IEEE80211_DEV(hw, &pdev->dev);
1890 pci_set_drvdata(pdev, hw);
1891
1892 rtlpriv = hw->priv;
1893 rtlpriv->hw = hw;
1894 pcipriv = (void *)rtlpriv->priv;
1895 pcipriv->dev.pdev = pdev;
1896 init_completion(&rtlpriv->firmware_loading_complete);
1897
1898 /* init cfg & intf_ops */
1899 rtlpriv->rtlhal.interface = INTF_PCI;
1900 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1901 rtlpriv->intf_ops = &rtl_pci_ops;
1902 rtlpriv->glb_var = &global_var;
1903
1904 /*
1905 *init dbgp flags before all
1906 *other functions, because we will
1907 *use it in other funtions like
1908 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1909 *you can not use these macro
1910 *before this
1911 */
1912 rtl_dbgp_flag_init(hw);
1913
1914 /* MEM map */
1915 err = pci_request_regions(pdev, KBUILD_MODNAME);
1916 if (err) {
1917 RT_ASSERT(false, "Can't obtain PCI resources\n");
1918 goto fail1;
1919 }
1920
1921 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1922 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1923 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
1924
1925 /*shared mem start */
1926 rtlpriv->io.pci_mem_start =
1927 (unsigned long)pci_iomap(pdev,
1928 rtlpriv->cfg->bar_id, pmem_len);
1929 if (rtlpriv->io.pci_mem_start == 0) {
1930 RT_ASSERT(false, "Can't map PCI mem\n");
1931 err = -ENOMEM;
1932 goto fail2;
1933 }
1934
1935 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1936 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
1937 pmem_start, pmem_len, pmem_flags,
1938 rtlpriv->io.pci_mem_start);
1939
1940 /* Disable Clk Request */
1941 pci_write_config_byte(pdev, 0x81, 0);
1942 /* leave D3 mode */
1943 pci_write_config_byte(pdev, 0x44, 0);
1944 pci_write_config_byte(pdev, 0x04, 0x06);
1945 pci_write_config_byte(pdev, 0x04, 0x07);
1946
1947 /* find adapter */
1948 if (!_rtl_pci_find_adapter(pdev, hw)) {
1949 err = -ENODEV;
1950 goto fail3;
1951 }
1952
1953 /* Init IO handler */
1954 _rtl_pci_io_handler_init(&pdev->dev, hw);
1955
1956 /*like read eeprom and so on */
1957 rtlpriv->cfg->ops->read_eeprom_info(hw);
1958
1959 /*aspm */
1960 rtl_pci_init_aspm(hw);
1961
1962 /* Init mac80211 sw */
1963 err = rtl_init_core(hw);
1964 if (err) {
1965 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1966 "Can't allocate sw for mac80211\n");
1967 goto fail3;
1968 }
1969
1970 /* Init PCI sw */
1971 err = rtl_pci_init(hw, pdev);
1972 if (err) {
1973 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n");
1974 goto fail3;
1975 }
1976
1977 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1978 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n");
1979 err = -ENODEV;
1980 goto fail3;
1981 }
1982
1983 rtlpriv->cfg->ops->init_sw_leds(hw);
1984
1985 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1986 if (err) {
1987 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1988 "failed to create sysfs device attributes\n");
1989 goto fail3;
1990 }
1991
1992 rtlpci = rtl_pcidev(pcipriv);
1993 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1994 IRQF_SHARED, KBUILD_MODNAME, hw);
1995 if (err) {
1996 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1997 "%s: failed to register IRQ handler\n",
1998 wiphy_name(hw->wiphy));
1999 goto fail3;
2000 }
2001 rtlpci->irq_alloc = 1;
2002
2003 return 0;
2004
2005 fail3:
2006 rtl_deinit_core(hw);
2007
2008 if (rtlpriv->io.pci_mem_start != 0)
2009 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2010
2011 fail2:
2012 pci_release_regions(pdev);
2013 complete(&rtlpriv->firmware_loading_complete);
2014
2015 fail1:
2016 if (hw)
2017 ieee80211_free_hw(hw);
2018 pci_set_drvdata(pdev, NULL);
2019 pci_disable_device(pdev);
2020
2021 return err;
2022
2023 }
2024 EXPORT_SYMBOL(rtl_pci_probe);
2025
rtl_pci_disconnect(struct pci_dev * pdev)2026 void rtl_pci_disconnect(struct pci_dev *pdev)
2027 {
2028 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2029 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2030 struct rtl_priv *rtlpriv = rtl_priv(hw);
2031 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2032 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2033
2034 /* just in case driver is removed before firmware callback */
2035 wait_for_completion(&rtlpriv->firmware_loading_complete);
2036 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2037
2038 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
2039
2040 /*ieee80211_unregister_hw will call ops_stop */
2041 if (rtlmac->mac80211_registered == 1) {
2042 ieee80211_unregister_hw(hw);
2043 rtlmac->mac80211_registered = 0;
2044 } else {
2045 rtl_deinit_deferred_work(hw);
2046 rtlpriv->intf_ops->adapter_stop(hw);
2047 }
2048 rtlpriv->cfg->ops->disable_interrupt(hw);
2049
2050 /*deinit rfkill */
2051 rtl_deinit_rfkill(hw);
2052
2053 rtl_pci_deinit(hw);
2054 rtl_deinit_core(hw);
2055 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2056
2057 if (rtlpci->irq_alloc) {
2058 synchronize_irq(rtlpci->pdev->irq);
2059 free_irq(rtlpci->pdev->irq, hw);
2060 rtlpci->irq_alloc = 0;
2061 }
2062
2063 list_del(&rtlpriv->list);
2064 if (rtlpriv->io.pci_mem_start != 0) {
2065 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2066 pci_release_regions(pdev);
2067 }
2068
2069 pci_disable_device(pdev);
2070
2071 rtl_pci_disable_aspm(hw);
2072
2073 pci_set_drvdata(pdev, NULL);
2074
2075 ieee80211_free_hw(hw);
2076 }
2077 EXPORT_SYMBOL(rtl_pci_disconnect);
2078
2079 #ifdef CONFIG_PM_SLEEP
2080 /***************************************
2081 kernel pci power state define:
2082 PCI_D0 ((pci_power_t __force) 0)
2083 PCI_D1 ((pci_power_t __force) 1)
2084 PCI_D2 ((pci_power_t __force) 2)
2085 PCI_D3hot ((pci_power_t __force) 3)
2086 PCI_D3cold ((pci_power_t __force) 4)
2087 PCI_UNKNOWN ((pci_power_t __force) 5)
2088
2089 This function is called when system
2090 goes into suspend state mac80211 will
2091 call rtl_mac_stop() from the mac80211
2092 suspend function first, So there is
2093 no need to call hw_disable here.
2094 ****************************************/
rtl_pci_suspend(struct device * dev)2095 int rtl_pci_suspend(struct device *dev)
2096 {
2097 struct pci_dev *pdev = to_pci_dev(dev);
2098 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2099 struct rtl_priv *rtlpriv = rtl_priv(hw);
2100
2101 rtlpriv->cfg->ops->hw_suspend(hw);
2102 rtl_deinit_rfkill(hw);
2103
2104 return 0;
2105 }
2106 EXPORT_SYMBOL(rtl_pci_suspend);
2107
rtl_pci_resume(struct device * dev)2108 int rtl_pci_resume(struct device *dev)
2109 {
2110 struct pci_dev *pdev = to_pci_dev(dev);
2111 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2112 struct rtl_priv *rtlpriv = rtl_priv(hw);
2113
2114 rtlpriv->cfg->ops->hw_resume(hw);
2115 rtl_init_rfkill(hw);
2116 return 0;
2117 }
2118 EXPORT_SYMBOL(rtl_pci_resume);
2119 #endif /* CONFIG_PM_SLEEP */
2120
2121 struct rtl_intf_ops rtl_pci_ops = {
2122 .read_efuse_byte = read_efuse_byte,
2123 .adapter_start = rtl_pci_start,
2124 .adapter_stop = rtl_pci_stop,
2125 .check_buddy_priv = rtl_pci_check_buddy_priv,
2126 .adapter_tx = rtl_pci_tx,
2127 .flush = rtl_pci_flush,
2128 .reset_trx_ring = rtl_pci_reset_trx_ring,
2129 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2130
2131 .disable_aspm = rtl_pci_disable_aspm,
2132 .enable_aspm = rtl_pci_enable_aspm,
2133 };
2134