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/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
Diop_version_defs.h15 #define REG_RD( scope, inst, reg ) \ argument
21 #define REG_WR( scope, inst, reg, val ) \ argument
27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
41 #define REG_RD_INT( scope, inst, reg ) \ argument
46 #define REG_WR_INT( scope, inst, reg, val ) \ argument
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ argument
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ argument
72 #define REG_ADDR( scope, inst, reg ) \ argument
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Diop_sap_in_defs.h15 #define REG_RD( scope, inst, reg ) \ argument
21 #define REG_WR( scope, inst, reg, val ) \ argument
27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
41 #define REG_RD_INT( scope, inst, reg ) \ argument
46 #define REG_WR_INT( scope, inst, reg, val ) \ argument
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ argument
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ argument
72 #define REG_ADDR( scope, inst, reg ) \ argument
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
/arch/cris/include/arch-v32/arch/hwregs/iop/
Diop_version_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
24 #define REG_WR( scope, inst, reg, val ) \ argument
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
44 #define REG_RD_INT( scope, inst, reg ) \ argument
49 #define REG_WR_INT( scope, inst, reg, val ) \ argument
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ argument
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ argument
75 #define REG_ADDR( scope, inst, reg ) \ argument
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Diop_scrc_out_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
24 #define REG_WR( scope, inst, reg, val ) \ argument
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
44 #define REG_RD_INT( scope, inst, reg ) \ argument
49 #define REG_WR_INT( scope, inst, reg, val ) \ argument
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ argument
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ argument
75 #define REG_ADDR( scope, inst, reg ) \ argument
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Diop_scrc_in_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
24 #define REG_WR( scope, inst, reg, val ) \ argument
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
44 #define REG_RD_INT( scope, inst, reg ) \ argument
49 #define REG_WR_INT( scope, inst, reg, val ) \ argument
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ argument
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ argument
75 #define REG_ADDR( scope, inst, reg ) \ argument
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Diop_fifo_out_extra_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
24 #define REG_WR( scope, inst, reg, val ) \ argument
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
44 #define REG_RD_INT( scope, inst, reg ) \ argument
49 #define REG_WR_INT( scope, inst, reg, val ) \ argument
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ argument
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ argument
75 #define REG_ADDR( scope, inst, reg ) \ argument
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Diop_fifo_in_extra_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
24 #define REG_WR( scope, inst, reg, val ) \ argument
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
44 #define REG_RD_INT( scope, inst, reg ) \ argument
49 #define REG_WR_INT( scope, inst, reg, val ) \ argument
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ argument
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ argument
75 #define REG_ADDR( scope, inst, reg ) \ argument
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
/arch/cris/include/arch-v32/arch/hwregs/
Dirq_nmi_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
24 #define REG_WR( scope, inst, reg, val ) \ argument
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
44 #define REG_RD_INT( scope, inst, reg ) \ argument
49 #define REG_WR_INT( scope, inst, reg, val ) \ argument
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ argument
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ argument
75 #define REG_ADDR( scope, inst, reg ) \ argument
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Dstrcop_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
24 #define REG_WR( scope, inst, reg, val ) \ argument
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
44 #define REG_RD_INT( scope, inst, reg ) \ argument
49 #define REG_WR_INT( scope, inst, reg, val ) \ argument
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ argument
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ argument
75 #define REG_ADDR( scope, inst, reg ) \ argument
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Dconfig_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
24 #define REG_WR( scope, inst, reg, val ) \ argument
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
44 #define REG_RD_INT( scope, inst, reg ) \ argument
49 #define REG_WR_INT( scope, inst, reg, val ) \ argument
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ argument
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ argument
75 #define REG_ADDR( scope, inst, reg ) \ argument
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Drt_trace_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
24 #define REG_WR( scope, inst, reg, val ) \ argument
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
44 #define REG_RD_INT( scope, inst, reg ) \ argument
49 #define REG_WR_INT( scope, inst, reg, val ) \ argument
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ argument
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ argument
75 #define REG_ADDR( scope, inst, reg ) \ argument
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/
Diop_version_defs_asm.h15 #define REG_FIELD( scope, reg, field, value ) \ argument
21 #define REG_STATE( scope, reg, field, symbolic_value ) \ argument
27 #define REG_MASK( scope, reg, field ) \ argument
33 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb argument
37 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit argument
41 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) argument
46 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Diop_sap_in_defs_asm.h15 #define REG_FIELD( scope, reg, field, value ) \ argument
21 #define REG_STATE( scope, reg, field, symbolic_value ) \ argument
27 #define REG_MASK( scope, reg, field ) \ argument
33 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb argument
37 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit argument
41 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) argument
46 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
/arch/cris/include/arch-v32/arch/hwregs/iop/asm/
Diop_version_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \ argument
24 #define REG_STATE( scope, reg, field, symbolic_value ) \ argument
30 #define REG_MASK( scope, reg, field ) \ argument
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb argument
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit argument
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) argument
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Diop_scrc_in_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \ argument
24 #define REG_STATE( scope, reg, field, symbolic_value ) \ argument
30 #define REG_MASK( scope, reg, field ) \ argument
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb argument
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit argument
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) argument
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Diop_scrc_out_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \ argument
24 #define REG_STATE( scope, reg, field, symbolic_value ) \ argument
30 #define REG_MASK( scope, reg, field ) \ argument
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb argument
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit argument
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) argument
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
/arch/cris/include/arch-v32/arch/hwregs/asm/
Dirq_nmi_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \ argument
24 #define REG_STATE( scope, reg, field, symbolic_value ) \ argument
30 #define REG_MASK( scope, reg, field ) \ argument
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb argument
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit argument
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) argument
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Dstrcop_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \ argument
24 #define REG_STATE( scope, reg, field, symbolic_value ) \ argument
30 #define REG_MASK( scope, reg, field ) \ argument
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb argument
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit argument
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) argument
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Dcris_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \ argument
24 #define REG_STATE( scope, reg, field, symbolic_value ) \ argument
30 #define REG_MASK( scope, reg, field ) \ argument
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb argument
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit argument
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) argument
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Dstrmux_defs_asm.h18 #define REG_FIELD( scope, reg, field, value ) \ argument
24 #define REG_STATE( scope, reg, field, symbolic_value ) \ argument
30 #define REG_MASK( scope, reg, field ) \ argument
36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb argument
40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit argument
44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) argument
49 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
Dstrmux_defs.h15 #define REG_RD( scope, inst, reg ) \ argument
21 #define REG_WR( scope, inst, reg, val ) \ argument
27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
41 #define REG_RD_INT( scope, inst, reg ) \ argument
46 #define REG_WR_INT( scope, inst, reg, val ) \ argument
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ argument
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ argument
72 #define REG_ADDR( scope, inst, reg ) \ argument
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Dl2cache_defs.h15 #define REG_RD( scope, inst, reg ) \ argument
21 #define REG_WR( scope, inst, reg, val ) \ argument
27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
41 #define REG_RD_INT( scope, inst, reg ) \ argument
46 #define REG_WR_INT( scope, inst, reg, val ) \ argument
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ argument
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ argument
72 #define REG_ADDR( scope, inst, reg ) \ argument
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Dclkgen_defs.h15 #define REG_RD( scope, inst, reg ) \ argument
21 #define REG_WR( scope, inst, reg, val ) \ argument
27 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
41 #define REG_RD_INT( scope, inst, reg ) \ argument
46 #define REG_WR_INT( scope, inst, reg, val ) \ argument
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ argument
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ argument
72 #define REG_ADDR( scope, inst, reg ) \ argument
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
Dstrmux_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
24 #define REG_WR( scope, inst, reg, val ) \ argument
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
44 #define REG_RD_INT( scope, inst, reg ) \ argument
49 #define REG_WR_INT( scope, inst, reg, val ) \ argument
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ argument
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ argument
75 #define REG_ADDR( scope, inst, reg ) \ argument
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument
Dconfig_defs.h18 #define REG_RD( scope, inst, reg ) \ argument
24 #define REG_WR( scope, inst, reg, val ) \ argument
30 #define REG_RD_VECT( scope, inst, reg, index ) \ argument
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ argument
44 #define REG_RD_INT( scope, inst, reg ) \ argument
49 #define REG_WR_INT( scope, inst, reg, val ) \ argument
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ argument
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ argument
75 #define REG_ADDR( scope, inst, reg ) \ argument
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ argument

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