1 /*
2 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #ifndef FIMC_CORE_H_
10 #define FIMC_CORE_H_
11
12 /*#define DEBUG*/
13
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/sched.h>
17 #include <linux/spinlock.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/types.h>
20 #include <linux/videodev2.h>
21 #include <linux/io.h>
22 #include <linux/sizes.h>
23
24 #include <media/media-entity.h>
25 #include <media/videobuf2-core.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-mem2mem.h>
29 #include <media/v4l2-mediabus.h>
30 #include <media/s5p_fimc.h>
31
32 #define dbg(fmt, args...) \
33 pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
34
35 /* Time to wait for next frame VSYNC interrupt while stopping operation. */
36 #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
37 #define MAX_FIMC_CLOCKS 2
38 #define FIMC_DRIVER_NAME "exynos4-fimc"
39 #define FIMC_MAX_DEVS 4
40 #define FIMC_MAX_OUT_BUFS 4
41 #define SCALER_MAX_HRATIO 64
42 #define SCALER_MAX_VRATIO 64
43 #define DMA_MIN_SIZE 8
44 #define FIMC_CAMIF_MAX_HEIGHT 0x2000
45 #define FIMC_MAX_JPEG_BUF_SIZE (10 * SZ_1M)
46 #define FIMC_MAX_PLANES 3
47 #define FIMC_PIX_LIMITS_MAX 4
48 #define FIMC_DEF_MIN_SIZE 16
49 #define FIMC_DEF_HEIGHT_ALIGN 2
50 #define FIMC_DEF_HOR_OFFS_ALIGN 1
51
52 /* indices to the clocks array */
53 enum {
54 CLK_BUS,
55 CLK_GATE,
56 };
57
58 enum fimc_dev_flags {
59 ST_LPM,
60 /* m2m node */
61 ST_M2M_RUN,
62 ST_M2M_PEND,
63 ST_M2M_SUSPENDING,
64 ST_M2M_SUSPENDED,
65 /* capture node */
66 ST_CAPT_PEND,
67 ST_CAPT_RUN,
68 ST_CAPT_STREAM,
69 ST_CAPT_ISP_STREAM,
70 ST_CAPT_SUSPENDED,
71 ST_CAPT_SHUT,
72 ST_CAPT_BUSY,
73 ST_CAPT_APPLY_CFG,
74 ST_CAPT_JPEG,
75 };
76
77 #define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)
78 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
79
80 #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
81 #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
82 #define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)
83
84 enum fimc_datapath {
85 FIMC_IO_NONE,
86 FIMC_IO_CAMERA,
87 FIMC_IO_DMA,
88 FIMC_IO_LCDFIFO,
89 FIMC_IO_WRITEBACK,
90 FIMC_IO_ISP,
91 };
92
93 enum fimc_color_fmt {
94 FIMC_FMT_RGB444 = 0x10,
95 FIMC_FMT_RGB555,
96 FIMC_FMT_RGB565,
97 FIMC_FMT_RGB666,
98 FIMC_FMT_RGB888,
99 FIMC_FMT_RGB30_LOCAL,
100 FIMC_FMT_YCBCR420 = 0x20,
101 FIMC_FMT_YCBYCR422,
102 FIMC_FMT_YCRYCB422,
103 FIMC_FMT_CBYCRY422,
104 FIMC_FMT_CRYCBY422,
105 FIMC_FMT_YCBCR444_LOCAL,
106 FIMC_FMT_RAW8 = 0x40,
107 FIMC_FMT_RAW10,
108 FIMC_FMT_RAW12,
109 FIMC_FMT_JPEG = 0x80,
110 FIMC_FMT_YUYV_JPEG = 0x100,
111 };
112
113 #define fimc_fmt_is_user_defined(x) (!!((x) & 0x180))
114 #define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
115
116 #define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \
117 __strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
118
119 /* The hardware context state. */
120 #define FIMC_PARAMS (1 << 0)
121 #define FIMC_COMPOSE (1 << 1)
122 #define FIMC_CTX_M2M (1 << 16)
123 #define FIMC_CTX_CAP (1 << 17)
124 #define FIMC_CTX_SHUT (1 << 18)
125
126 /* Image conversion flags */
127 #define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
128 #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
129 #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
130 #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
131 #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
132 #define FIMC_SCAN_MODE_INTERLACED (1 << 2)
133 /*
134 * YCbCr data dynamic range for RGB-YUV color conversion.
135 * Y/Cb/Cr: (0 ~ 255) */
136 #define FIMC_COLOR_RANGE_WIDE (0 << 3)
137 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
138 #define FIMC_COLOR_RANGE_NARROW (1 << 3)
139
140 /**
141 * struct fimc_dma_offset - pixel offset information for DMA
142 * @y_h: y value horizontal offset
143 * @y_v: y value vertical offset
144 * @cb_h: cb value horizontal offset
145 * @cb_v: cb value vertical offset
146 * @cr_h: cr value horizontal offset
147 * @cr_v: cr value vertical offset
148 */
149 struct fimc_dma_offset {
150 int y_h;
151 int y_v;
152 int cb_h;
153 int cb_v;
154 int cr_h;
155 int cr_v;
156 };
157
158 /**
159 * struct fimc_effect - color effect information
160 * @type: effect type
161 * @pat_cb: cr value when type is "arbitrary"
162 * @pat_cr: cr value when type is "arbitrary"
163 */
164 struct fimc_effect {
165 u32 type;
166 u8 pat_cb;
167 u8 pat_cr;
168 };
169
170 /**
171 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
172 * @scaleup_h: flag indicating scaling up horizontally
173 * @scaleup_v: flag indicating scaling up vertically
174 * @copy_mode: flag indicating transparent DMA transfer (no scaling
175 * and color format conversion)
176 * @enabled: flag indicating if the scaler is used
177 * @hfactor: horizontal shift factor
178 * @vfactor: vertical shift factor
179 * @pre_hratio: horizontal ratio of the prescaler
180 * @pre_vratio: vertical ratio of the prescaler
181 * @pre_dst_width: the prescaler's destination width
182 * @pre_dst_height: the prescaler's destination height
183 * @main_hratio: the main scaler's horizontal ratio
184 * @main_vratio: the main scaler's vertical ratio
185 * @real_width: source pixel (width - offset)
186 * @real_height: source pixel (height - offset)
187 */
188 struct fimc_scaler {
189 unsigned int scaleup_h:1;
190 unsigned int scaleup_v:1;
191 unsigned int copy_mode:1;
192 unsigned int enabled:1;
193 u32 hfactor;
194 u32 vfactor;
195 u32 pre_hratio;
196 u32 pre_vratio;
197 u32 pre_dst_width;
198 u32 pre_dst_height;
199 u32 main_hratio;
200 u32 main_vratio;
201 u32 real_width;
202 u32 real_height;
203 };
204
205 /**
206 * struct fimc_addr - the FIMC physical address set for DMA
207 * @y: luminance plane physical address
208 * @cb: Cb plane physical address
209 * @cr: Cr plane physical address
210 */
211 struct fimc_addr {
212 u32 y;
213 u32 cb;
214 u32 cr;
215 };
216
217 /**
218 * struct fimc_vid_buffer - the driver's video buffer
219 * @vb: v4l videobuf buffer
220 * @list: linked list structure for buffer queue
221 * @paddr: precalculated physical address set
222 * @index: buffer index for the output DMA engine
223 */
224 struct fimc_vid_buffer {
225 struct vb2_buffer vb;
226 struct list_head list;
227 struct fimc_addr paddr;
228 int index;
229 };
230
231 /**
232 * struct fimc_frame - source/target frame properties
233 * @f_width: image full width (virtual screen size)
234 * @f_height: image full height (virtual screen size)
235 * @o_width: original image width as set by S_FMT
236 * @o_height: original image height as set by S_FMT
237 * @offs_h: image horizontal pixel offset
238 * @offs_v: image vertical pixel offset
239 * @width: image pixel width
240 * @height: image pixel weight
241 * @payload: image size in bytes (w x h x bpp)
242 * @bytesperline: bytesperline value for each plane
243 * @paddr: image frame buffer physical addresses
244 * @dma_offset: DMA offset in bytes
245 * @fmt: fimc color format pointer
246 */
247 struct fimc_frame {
248 u32 f_width;
249 u32 f_height;
250 u32 o_width;
251 u32 o_height;
252 u32 offs_h;
253 u32 offs_v;
254 u32 width;
255 u32 height;
256 unsigned int payload[VIDEO_MAX_PLANES];
257 unsigned int bytesperline[VIDEO_MAX_PLANES];
258 struct fimc_addr paddr;
259 struct fimc_dma_offset dma_offset;
260 struct fimc_fmt *fmt;
261 u8 alpha;
262 };
263
264 /**
265 * struct fimc_m2m_device - v4l2 memory-to-memory device data
266 * @vfd: the video device node for v4l2 m2m mode
267 * @m2m_dev: v4l2 memory-to-memory device data
268 * @ctx: hardware context data
269 * @refcnt: the reference counter
270 */
271 struct fimc_m2m_device {
272 struct video_device vfd;
273 struct v4l2_m2m_dev *m2m_dev;
274 struct fimc_ctx *ctx;
275 int refcnt;
276 };
277
278 #define FIMC_SD_PAD_SINK_CAM 0
279 #define FIMC_SD_PAD_SINK_FIFO 1
280 #define FIMC_SD_PAD_SOURCE 2
281 #define FIMC_SD_PADS_NUM 3
282
283 /**
284 * struct fimc_vid_cap - camera capture device information
285 * @ctx: hardware context data
286 * @vfd: video device node for camera capture mode
287 * @subdev: subdev exposing the FIMC processing block
288 * @vd_pad: fimc video capture node pad
289 * @sd_pads: fimc video processing block pads
290 * @ci_fmt: image format at the FIMC camera input (and the scaler output)
291 * @wb_fmt: image format at the FIMC ISP Writeback input
292 * @source_config: external image source related configuration structure
293 * @pending_buf_q: the pending buffer queue head
294 * @active_buf_q: the queue head of buffers scheduled in hardware
295 * @vbq: the capture am video buffer queue
296 * @active_buf_cnt: number of video buffers scheduled in hardware
297 * @buf_index: index for managing the output DMA buffers
298 * @frame_count: the frame counter for statistics
299 * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
300 * @input_index: input (camera sensor) index
301 * @refcnt: driver's private reference counter
302 * @input: capture input type, grp_id of the attached subdev
303 * @user_subdev_api: true if subdevs are not configured by the host driver
304 */
305 struct fimc_vid_cap {
306 struct fimc_ctx *ctx;
307 struct vb2_alloc_ctx *alloc_ctx;
308 struct video_device vfd;
309 struct v4l2_subdev subdev;
310 struct media_pad vd_pad;
311 struct media_pad sd_pads[FIMC_SD_PADS_NUM];
312 struct v4l2_mbus_framefmt ci_fmt;
313 struct v4l2_mbus_framefmt wb_fmt;
314 struct fimc_source_info source_config;
315 struct list_head pending_buf_q;
316 struct list_head active_buf_q;
317 struct vb2_queue vbq;
318 int active_buf_cnt;
319 int buf_index;
320 unsigned int frame_count;
321 unsigned int reqbufs_count;
322 bool streaming;
323 int input_index;
324 int refcnt;
325 u32 input;
326 bool user_subdev_api;
327 };
328
329 /**
330 * struct fimc_pix_limit - image pixel size limits in various IP configurations
331 *
332 * @scaler_en_w: max input pixel width when the scaler is enabled
333 * @scaler_dis_w: max input pixel width when the scaler is disabled
334 * @in_rot_en_h: max input width with the input rotator is on
335 * @in_rot_dis_w: max input width with the input rotator is off
336 * @out_rot_en_w: max output width with the output rotator on
337 * @out_rot_dis_w: max output width with the output rotator off
338 */
339 struct fimc_pix_limit {
340 u16 scaler_en_w;
341 u16 scaler_dis_w;
342 u16 in_rot_en_h;
343 u16 in_rot_dis_w;
344 u16 out_rot_en_w;
345 u16 out_rot_dis_w;
346 };
347
348 /**
349 * struct fimc_variant - FIMC device variant information
350 * @has_inp_rot: set if has input rotator
351 * @has_out_rot: set if has output rotator
352 * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
353 * are present in this IP revision
354 * @has_cam_if: set if this instance has a camera input interface
355 * @has_isp_wb: set if this instance has ISP writeback input
356 * @pix_limit: pixel size constraints for the scaler
357 * @min_inp_pixsize: minimum input pixel size
358 * @min_out_pixsize: minimum output pixel size
359 * @hor_offs_align: horizontal pixel offset aligment
360 * @min_vsize_align: minimum vertical pixel size alignment
361 */
362 struct fimc_variant {
363 unsigned int has_inp_rot:1;
364 unsigned int has_out_rot:1;
365 unsigned int has_mainscaler_ext:1;
366 unsigned int has_cam_if:1;
367 unsigned int has_isp_wb:1;
368 const struct fimc_pix_limit *pix_limit;
369 u16 min_inp_pixsize;
370 u16 min_out_pixsize;
371 u16 hor_offs_align;
372 u16 min_vsize_align;
373 };
374
375 /**
376 * struct fimc_drvdata - per device type driver data
377 * @variant: variant information for this device
378 * @num_entities: number of fimc instances available in a SoC
379 * @lclk_frequency: local bus clock frequency
380 * @cistatus2: 1 if the FIMC IPs have CISTATUS2 register
381 * @dma_pix_hoff: the horizontal DMA offset unit: 1 - pixels, 0 - bytes
382 * @alpha_color: 1 if alpha color component is supported
383 * @out_buf_count: maximum number of output DMA buffers supported
384 */
385 struct fimc_drvdata {
386 const struct fimc_variant *variant[FIMC_MAX_DEVS];
387 int num_entities;
388 unsigned long lclk_frequency;
389 /* Fields common to all FIMC IP instances */
390 u8 cistatus2;
391 u8 dma_pix_hoff;
392 u8 alpha_color;
393 u8 out_buf_count;
394 };
395
396 #define fimc_get_drvdata(_pdev) \
397 ((struct fimc_drvdata *) platform_get_device_id(_pdev)->driver_data)
398
399 struct fimc_ctx;
400
401 /**
402 * struct fimc_dev - abstraction for FIMC entity
403 * @slock: the spinlock protecting this data structure
404 * @lock: the mutex protecting this data structure
405 * @pdev: pointer to the FIMC platform device
406 * @pdata: pointer to the device platform data
407 * @sysreg: pointer to the SYSREG regmap
408 * @variant: the IP variant information
409 * @id: FIMC device index (0..FIMC_MAX_DEVS)
410 * @clock: clocks required for FIMC operation
411 * @regs: the mapped hardware registers
412 * @irq_queue: interrupt handler waitqueue
413 * @v4l2_dev: root v4l2_device
414 * @m2m: memory-to-memory V4L2 device information
415 * @vid_cap: camera capture device information
416 * @state: flags used to synchronize m2m and capture mode operation
417 * @alloc_ctx: videobuf2 memory allocator context
418 * @pipeline: fimc video capture pipeline data structure
419 */
420 struct fimc_dev {
421 spinlock_t slock;
422 struct mutex lock;
423 struct platform_device *pdev;
424 struct s5p_platform_fimc *pdata;
425 struct regmap *sysreg;
426 const struct fimc_variant *variant;
427 const struct fimc_drvdata *drv_data;
428 int id;
429 struct clk *clock[MAX_FIMC_CLOCKS];
430 void __iomem *regs;
431 wait_queue_head_t irq_queue;
432 struct v4l2_device *v4l2_dev;
433 struct fimc_m2m_device m2m;
434 struct fimc_vid_cap vid_cap;
435 unsigned long state;
436 struct vb2_alloc_ctx *alloc_ctx;
437 struct fimc_pipeline pipeline;
438 const struct fimc_pipeline_ops *pipeline_ops;
439 };
440
441 /**
442 * struct fimc_ctrls - v4l2 controls structure
443 * @handler: the control handler
444 * @colorfx: image effect control
445 * @colorfx_cbcr: Cb/Cr coefficients control
446 * @rotate: image rotation control
447 * @hflip: horizontal flip control
448 * @vflip: vertical flip control
449 * @alpha: RGB alpha control
450 * @ready: true if @handler is initialized
451 */
452 struct fimc_ctrls {
453 struct v4l2_ctrl_handler handler;
454 struct {
455 struct v4l2_ctrl *colorfx;
456 struct v4l2_ctrl *colorfx_cbcr;
457 };
458 struct v4l2_ctrl *rotate;
459 struct v4l2_ctrl *hflip;
460 struct v4l2_ctrl *vflip;
461 struct v4l2_ctrl *alpha;
462 bool ready;
463 };
464
465 /**
466 * fimc_ctx - the device context data
467 * @s_frame: source frame properties
468 * @d_frame: destination frame properties
469 * @out_order_1p: output 1-plane YCBCR order
470 * @out_order_2p: output 2-plane YCBCR order
471 * @in_order_1p input 1-plane YCBCR order
472 * @in_order_2p: input 2-plane YCBCR order
473 * @in_path: input mode (DMA or camera)
474 * @out_path: output mode (DMA or FIFO)
475 * @scaler: image scaler properties
476 * @effect: image effect
477 * @rotation: image clockwise rotation in degrees
478 * @hflip: indicates image horizontal flip if set
479 * @vflip: indicates image vertical flip if set
480 * @flags: additional flags for image conversion
481 * @state: flags to keep track of user configuration
482 * @fimc_dev: the FIMC device this context applies to
483 * @m2m_ctx: memory-to-memory device context
484 * @fh: v4l2 file handle
485 * @ctrls: v4l2 controls structure
486 */
487 struct fimc_ctx {
488 struct fimc_frame s_frame;
489 struct fimc_frame d_frame;
490 u32 out_order_1p;
491 u32 out_order_2p;
492 u32 in_order_1p;
493 u32 in_order_2p;
494 enum fimc_datapath in_path;
495 enum fimc_datapath out_path;
496 struct fimc_scaler scaler;
497 struct fimc_effect effect;
498 int rotation;
499 unsigned int hflip:1;
500 unsigned int vflip:1;
501 u32 flags;
502 u32 state;
503 struct fimc_dev *fimc_dev;
504 struct v4l2_m2m_ctx *m2m_ctx;
505 struct v4l2_fh fh;
506 struct fimc_ctrls ctrls;
507 };
508
509 #define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh)
510
set_frame_bounds(struct fimc_frame * f,u32 width,u32 height)511 static inline void set_frame_bounds(struct fimc_frame *f, u32 width, u32 height)
512 {
513 f->o_width = width;
514 f->o_height = height;
515 f->f_width = width;
516 f->f_height = height;
517 }
518
set_frame_crop(struct fimc_frame * f,u32 left,u32 top,u32 width,u32 height)519 static inline void set_frame_crop(struct fimc_frame *f,
520 u32 left, u32 top, u32 width, u32 height)
521 {
522 f->offs_h = left;
523 f->offs_v = top;
524 f->width = width;
525 f->height = height;
526 }
527
fimc_get_format_depth(struct fimc_fmt * ff)528 static inline u32 fimc_get_format_depth(struct fimc_fmt *ff)
529 {
530 u32 i, depth = 0;
531
532 if (ff != NULL)
533 for (i = 0; i < ff->colplanes; i++)
534 depth += ff->depth[i];
535 return depth;
536 }
537
fimc_capture_active(struct fimc_dev * fimc)538 static inline bool fimc_capture_active(struct fimc_dev *fimc)
539 {
540 unsigned long flags;
541 bool ret;
542
543 spin_lock_irqsave(&fimc->slock, flags);
544 ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
545 fimc->state & (1 << ST_CAPT_PEND));
546 spin_unlock_irqrestore(&fimc->slock, flags);
547 return ret;
548 }
549
fimc_ctx_state_set(u32 state,struct fimc_ctx * ctx)550 static inline void fimc_ctx_state_set(u32 state, struct fimc_ctx *ctx)
551 {
552 unsigned long flags;
553
554 spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
555 ctx->state |= state;
556 spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
557 }
558
fimc_ctx_state_is_set(u32 mask,struct fimc_ctx * ctx)559 static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
560 {
561 unsigned long flags;
562 bool ret;
563
564 spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
565 ret = (ctx->state & mask) == mask;
566 spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
567 return ret;
568 }
569
tiled_fmt(struct fimc_fmt * fmt)570 static inline int tiled_fmt(struct fimc_fmt *fmt)
571 {
572 return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
573 }
574
fimc_jpeg_fourcc(u32 pixelformat)575 static inline bool fimc_jpeg_fourcc(u32 pixelformat)
576 {
577 return (pixelformat == V4L2_PIX_FMT_JPEG ||
578 pixelformat == V4L2_PIX_FMT_S5C_UYVY_JPG);
579 }
580
fimc_user_defined_mbus_fmt(u32 code)581 static inline bool fimc_user_defined_mbus_fmt(u32 code)
582 {
583 return (code == V4L2_MBUS_FMT_JPEG_1X8 ||
584 code == V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8);
585 }
586
587 /* Return the alpha component bit mask */
fimc_get_alpha_mask(struct fimc_fmt * fmt)588 static inline int fimc_get_alpha_mask(struct fimc_fmt *fmt)
589 {
590 switch (fmt->color) {
591 case FIMC_FMT_RGB444: return 0x0f;
592 case FIMC_FMT_RGB555: return 0x01;
593 case FIMC_FMT_RGB888: return 0xff;
594 default: return 0;
595 };
596 }
597
ctx_get_frame(struct fimc_ctx * ctx,enum v4l2_buf_type type)598 static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
599 enum v4l2_buf_type type)
600 {
601 struct fimc_frame *frame;
602
603 if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
604 if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
605 frame = &ctx->s_frame;
606 else
607 return ERR_PTR(-EINVAL);
608 } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
609 frame = &ctx->d_frame;
610 } else {
611 v4l2_err(ctx->fimc_dev->v4l2_dev,
612 "Wrong buffer/video queue type (%d)\n", type);
613 return ERR_PTR(-EINVAL);
614 }
615
616 return frame;
617 }
618
619 /* -----------------------------------------------------*/
620 /* fimc-core.c */
621 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
622 struct v4l2_fmtdesc *f);
623 void __fimc_vidioc_querycap(struct device *dev, struct v4l2_capability *cap,
624 unsigned int caps);
625 int fimc_ctrls_create(struct fimc_ctx *ctx);
626 void fimc_ctrls_delete(struct fimc_ctx *ctx);
627 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active);
628 void fimc_alpha_ctrl_update(struct fimc_ctx *ctx);
629 void __fimc_get_format(struct fimc_frame *frame, struct v4l2_format *f);
630 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
631 struct v4l2_pix_format_mplane *pix);
632 struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code,
633 unsigned int mask, int index);
634 struct fimc_fmt *fimc_get_format(unsigned int index);
635
636 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
637 int dw, int dh, int rotation);
638 int fimc_set_scaler_info(struct fimc_ctx *ctx);
639 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
640 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
641 struct fimc_frame *frame, struct fimc_addr *paddr);
642 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f);
643 void fimc_set_yuv_order(struct fimc_ctx *ctx);
644 void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf);
645
646 int fimc_register_m2m_device(struct fimc_dev *fimc,
647 struct v4l2_device *v4l2_dev);
648 void fimc_unregister_m2m_device(struct fimc_dev *fimc);
649 int fimc_register_driver(void);
650 void fimc_unregister_driver(void);
651
652 #ifdef CONFIG_MFD_SYSCON
fimc_get_sysreg_regmap(struct device_node * node)653 static inline struct regmap * fimc_get_sysreg_regmap(struct device_node *node)
654 {
655 return syscon_regmap_lookup_by_phandle(node, "samsung,sysreg");
656 }
657 #else
658 #define fimc_get_sysreg_regmap(node) (NULL)
659 #endif
660
661 /* -----------------------------------------------------*/
662 /* fimc-m2m.c */
663 void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state);
664
665 /* -----------------------------------------------------*/
666 /* fimc-capture.c */
667 int fimc_initialize_capture_subdev(struct fimc_dev *fimc);
668 void fimc_unregister_capture_subdev(struct fimc_dev *fimc);
669 int fimc_capture_ctrls_create(struct fimc_dev *fimc);
670 void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification,
671 void *arg);
672 int fimc_capture_suspend(struct fimc_dev *fimc);
673 int fimc_capture_resume(struct fimc_dev *fimc);
674
675 /*
676 * Buffer list manipulation functions. Must be called with fimc.slock held.
677 */
678
679 /**
680 * fimc_active_queue_add - add buffer to the capture active buffers queue
681 * @buf: buffer to add to the active buffers list
682 */
fimc_active_queue_add(struct fimc_vid_cap * vid_cap,struct fimc_vid_buffer * buf)683 static inline void fimc_active_queue_add(struct fimc_vid_cap *vid_cap,
684 struct fimc_vid_buffer *buf)
685 {
686 list_add_tail(&buf->list, &vid_cap->active_buf_q);
687 vid_cap->active_buf_cnt++;
688 }
689
690 /**
691 * fimc_active_queue_pop - pop buffer from the capture active buffers queue
692 *
693 * The caller must assure the active_buf_q list is not empty.
694 */
fimc_active_queue_pop(struct fimc_vid_cap * vid_cap)695 static inline struct fimc_vid_buffer *fimc_active_queue_pop(
696 struct fimc_vid_cap *vid_cap)
697 {
698 struct fimc_vid_buffer *buf;
699 buf = list_entry(vid_cap->active_buf_q.next,
700 struct fimc_vid_buffer, list);
701 list_del(&buf->list);
702 vid_cap->active_buf_cnt--;
703 return buf;
704 }
705
706 /**
707 * fimc_pending_queue_add - add buffer to the capture pending buffers queue
708 * @buf: buffer to add to the pending buffers list
709 */
fimc_pending_queue_add(struct fimc_vid_cap * vid_cap,struct fimc_vid_buffer * buf)710 static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
711 struct fimc_vid_buffer *buf)
712 {
713 list_add_tail(&buf->list, &vid_cap->pending_buf_q);
714 }
715
716 /**
717 * fimc_pending_queue_pop - pop buffer from the capture pending buffers queue
718 *
719 * The caller must assure the pending_buf_q list is not empty.
720 */
fimc_pending_queue_pop(struct fimc_vid_cap * vid_cap)721 static inline struct fimc_vid_buffer *fimc_pending_queue_pop(
722 struct fimc_vid_cap *vid_cap)
723 {
724 struct fimc_vid_buffer *buf;
725 buf = list_entry(vid_cap->pending_buf_q.next,
726 struct fimc_vid_buffer, list);
727 list_del(&buf->list);
728 return buf;
729 }
730
731 #endif /* FIMC_CORE_H_ */
732