1 /*
2 * arch/arm/mach-tegra/common.c
3 *
4 * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
5 * Copyright (C) 2010 Google, Inc.
6 *
7 * Author:
8 * Colin Cross <ccross@android.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
25 #include <linux/irqchip.h>
26 #include <linux/clk/tegra.h>
27
28 #include <asm/hardware/cache-l2x0.h>
29
30 #include "board.h"
31 #include "common.h"
32 #include "fuse.h"
33 #include "iomap.h"
34 #include "irq.h"
35 #include "pmc.h"
36 #include "apbio.h"
37 #include "sleep.h"
38 #include "pm.h"
39 #include "reset.h"
40
41 /*
42 * Storage for debug-macro.S's state.
43 *
44 * This must be in .data not .bss so that it gets initialized each time the
45 * kernel is loaded. The data is declared here rather than debug-macro.S so
46 * that multiple inclusions of debug-macro.S point at the same data.
47 */
48 u32 tegra_uart_config[4] = {
49 /* Debug UART initialization required */
50 1,
51 /* Debug UART physical address */
52 0,
53 /* Debug UART virtual address */
54 0,
55 /* Scratch space for debug macro */
56 0,
57 };
58
59 #ifdef CONFIG_OF
tegra_dt_init_irq(void)60 void __init tegra_dt_init_irq(void)
61 {
62 tegra_clocks_init();
63 tegra_pmc_init();
64 tegra_init_irq();
65 irqchip_init();
66 tegra_legacy_irq_syscore_init();
67 }
68 #endif
69
tegra_assert_system_reset(char mode,const char * cmd)70 void tegra_assert_system_reset(char mode, const char *cmd)
71 {
72 void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
73 u32 reg;
74
75 reg = readl_relaxed(reset);
76 reg |= 0x10;
77 writel_relaxed(reg, reset);
78 }
79
tegra_init_cache(void)80 static void __init tegra_init_cache(void)
81 {
82 #ifdef CONFIG_CACHE_L2X0
83 int ret;
84 void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
85 u32 aux_ctrl, cache_type;
86
87 cache_type = readl(p + L2X0_CACHE_TYPE);
88 aux_ctrl = (cache_type & 0x700) << (17-8);
89 aux_ctrl |= 0x7C400001;
90
91 ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
92 if (!ret)
93 l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
94 #endif
95
96 }
97
tegra_init_early(void)98 void __init tegra_init_early(void)
99 {
100 tegra_cpu_reset_handler_init();
101 tegra_apb_io_init();
102 tegra_init_fuse();
103 tegra_init_cache();
104 tegra_powergate_init();
105 tegra_hotplug_init();
106 }
107
tegra_init_late(void)108 void __init tegra_init_late(void)
109 {
110 tegra_init_suspend();
111 tegra_powergate_debugfs_init();
112 }
113