1 /*
2 * arch/arm/mach-tegra/fuse.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author:
8 * Colin Cross <ccross@android.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21 #include <linux/kernel.h>
22 #include <linux/io.h>
23 #include <linux/export.h>
24 #include <linux/tegra-soc.h>
25
26 #include "fuse.h"
27 #include "iomap.h"
28 #include "apbio.h"
29
30 #define FUSE_UID_LOW 0x108
31 #define FUSE_UID_HIGH 0x10c
32 #define FUSE_SKU_INFO 0x110
33
34 #define TEGRA20_FUSE_SPARE_BIT 0x200
35 #define TEGRA30_FUSE_SPARE_BIT 0x244
36
37 int tegra_sku_id;
38 int tegra_cpu_process_id;
39 int tegra_core_process_id;
40 int tegra_chip_id;
41 int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
42 int tegra_soc_speedo_id;
43 enum tegra_revision tegra_revision;
44
45 static int tegra_fuse_spare_bit;
46 static void (*tegra_init_speedo_data)(void);
47
48 /* The BCT to use at boot is specified by board straps that can be read
49 * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
50 */
51 int tegra_bct_strapping;
52
53 #define STRAP_OPT 0x008
54 #define GMI_AD0 (1 << 4)
55 #define GMI_AD1 (1 << 5)
56 #define RAM_ID_MASK (GMI_AD0 | GMI_AD1)
57 #define RAM_CODE_SHIFT 4
58
59 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
60 [TEGRA_REVISION_UNKNOWN] = "unknown",
61 [TEGRA_REVISION_A01] = "A01",
62 [TEGRA_REVISION_A02] = "A02",
63 [TEGRA_REVISION_A03] = "A03",
64 [TEGRA_REVISION_A03p] = "A03 prime",
65 [TEGRA_REVISION_A04] = "A04",
66 };
67
tegra_fuse_readl(unsigned long offset)68 u32 tegra_fuse_readl(unsigned long offset)
69 {
70 return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
71 }
72
tegra_spare_fuse(int bit)73 bool tegra_spare_fuse(int bit)
74 {
75 return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
76 }
77
tegra_get_revision(u32 id)78 static enum tegra_revision tegra_get_revision(u32 id)
79 {
80 u32 minor_rev = (id >> 16) & 0xf;
81
82 switch (minor_rev) {
83 case 1:
84 return TEGRA_REVISION_A01;
85 case 2:
86 return TEGRA_REVISION_A02;
87 case 3:
88 if (tegra_chip_id == TEGRA20 &&
89 (tegra_spare_fuse(18) || tegra_spare_fuse(19)))
90 return TEGRA_REVISION_A03p;
91 else
92 return TEGRA_REVISION_A03;
93 case 4:
94 return TEGRA_REVISION_A04;
95 default:
96 return TEGRA_REVISION_UNKNOWN;
97 }
98 }
99
tegra_get_process_id(void)100 static void tegra_get_process_id(void)
101 {
102 u32 reg;
103
104 reg = tegra_fuse_readl(tegra_fuse_spare_bit);
105 tegra_cpu_process_id = (reg >> 6) & 3;
106 reg = tegra_fuse_readl(tegra_fuse_spare_bit);
107 tegra_core_process_id = (reg >> 12) & 3;
108 }
109
tegra_read_chipid(void)110 u32 tegra_read_chipid(void)
111 {
112 return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
113 }
114
tegra_init_fuse(void)115 void tegra_init_fuse(void)
116 {
117 u32 id;
118
119 u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
120 reg |= 1 << 28;
121 writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
122
123 reg = tegra_fuse_readl(FUSE_SKU_INFO);
124 tegra_sku_id = reg & 0xFF;
125
126 reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
127 tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
128
129 id = tegra_read_chipid();
130 tegra_chip_id = (id >> 8) & 0xff;
131
132 switch (tegra_chip_id) {
133 case TEGRA20:
134 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
135 tegra_init_speedo_data = &tegra20_init_speedo_data;
136 break;
137 case TEGRA30:
138 tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
139 tegra_init_speedo_data = &tegra30_init_speedo_data;
140 break;
141 case TEGRA114:
142 tegra_init_speedo_data = &tegra114_init_speedo_data;
143 break;
144 default:
145 pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
146 tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
147 tegra_init_speedo_data = &tegra_get_process_id;
148 }
149
150 tegra_revision = tegra_get_revision(id);
151 tegra_init_speedo_data();
152
153 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
154 tegra_revision_name[tegra_revision],
155 tegra_sku_id, tegra_cpu_process_id,
156 tegra_core_process_id);
157 }
158
tegra_chip_uid(void)159 unsigned long long tegra_chip_uid(void)
160 {
161 unsigned long long lo, hi;
162
163 lo = tegra_fuse_readl(FUSE_UID_LOW);
164 hi = tegra_fuse_readl(FUSE_UID_HIGH);
165 return (hi << 32ull) | lo;
166 }
167 EXPORT_SYMBOL(tegra_chip_uid);
168