1 /*
2 * ti_hdmi_4xxx_ip.c
3 *
4 * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/err.h>
25 #include <linux/io.h>
26 #include <linux/interrupt.h>
27 #include <linux/mutex.h>
28 #include <linux/delay.h>
29 #include <linux/string.h>
30 #include <linux/seq_file.h>
31 #include <linux/gpio.h>
32 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
33 #include <sound/asound.h>
34 #include <sound/asoundef.h>
35 #endif
36
37 #include "ti_hdmi_4xxx_ip.h"
38 #include "dss.h"
39 #include "dss_features.h"
40
hdmi_write_reg(void __iomem * base_addr,const u16 idx,u32 val)41 static inline void hdmi_write_reg(void __iomem *base_addr,
42 const u16 idx, u32 val)
43 {
44 __raw_writel(val, base_addr + idx);
45 }
46
hdmi_read_reg(void __iomem * base_addr,const u16 idx)47 static inline u32 hdmi_read_reg(void __iomem *base_addr,
48 const u16 idx)
49 {
50 return __raw_readl(base_addr + idx);
51 }
52
hdmi_wp_base(struct hdmi_ip_data * ip_data)53 static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
54 {
55 return ip_data->base_wp;
56 }
57
hdmi_phy_base(struct hdmi_ip_data * ip_data)58 static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data)
59 {
60 return ip_data->base_wp + ip_data->phy_offset;
61 }
62
hdmi_pll_base(struct hdmi_ip_data * ip_data)63 static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data)
64 {
65 return ip_data->base_wp + ip_data->pll_offset;
66 }
67
hdmi_av_base(struct hdmi_ip_data * ip_data)68 static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data)
69 {
70 return ip_data->base_wp + ip_data->core_av_offset;
71 }
72
hdmi_core_sys_base(struct hdmi_ip_data * ip_data)73 static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
74 {
75 return ip_data->base_wp + ip_data->core_sys_offset;
76 }
77
hdmi_wait_for_bit_change(void __iomem * base_addr,const u16 idx,int b2,int b1,u32 val)78 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
79 const u16 idx,
80 int b2, int b1, u32 val)
81 {
82 u32 t = 0;
83 while (val != REG_GET(base_addr, idx, b2, b1)) {
84 udelay(1);
85 if (t++ > 10000)
86 return !val;
87 }
88 return val;
89 }
90
hdmi_pll_init(struct hdmi_ip_data * ip_data)91 static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
92 {
93 u32 r;
94 void __iomem *pll_base = hdmi_pll_base(ip_data);
95 struct hdmi_pll_info *fmt = &ip_data->pll_data;
96
97 /* PLL start always use manual mode */
98 REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
99
100 r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
101 r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
102 r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */
103
104 hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
105
106 r = hdmi_read_reg(pll_base, PLLCTRL_CFG2);
107
108 r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
109 r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
110 r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
111 r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
112
113 if (fmt->dcofreq) {
114 /* divider programming for frequency beyond 1000Mhz */
115 REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
116 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
117 } else {
118 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
119 }
120
121 hdmi_write_reg(pll_base, PLLCTRL_CFG2, r);
122
123 r = hdmi_read_reg(pll_base, PLLCTRL_CFG4);
124 r = FLD_MOD(r, fmt->regm2, 24, 18);
125 r = FLD_MOD(r, fmt->regmf, 17, 0);
126
127 hdmi_write_reg(pll_base, PLLCTRL_CFG4, r);
128
129 /* go now */
130 REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0);
131
132 /* wait for bit change */
133 if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO,
134 0, 0, 1) != 1) {
135 pr_err("PLL GO bit not set\n");
136 return -ETIMEDOUT;
137 }
138
139 /* Wait till the lock bit is set in PLL status */
140 if (hdmi_wait_for_bit_change(pll_base,
141 PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
142 pr_err("cannot lock PLL\n");
143 pr_err("CFG1 0x%x\n",
144 hdmi_read_reg(pll_base, PLLCTRL_CFG1));
145 pr_err("CFG2 0x%x\n",
146 hdmi_read_reg(pll_base, PLLCTRL_CFG2));
147 pr_err("CFG4 0x%x\n",
148 hdmi_read_reg(pll_base, PLLCTRL_CFG4));
149 return -ETIMEDOUT;
150 }
151
152 pr_debug("PLL locked!\n");
153
154 return 0;
155 }
156
157 /* PHY_PWR_CMD */
hdmi_set_phy_pwr(struct hdmi_ip_data * ip_data,enum hdmi_phy_pwr val)158 static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val)
159 {
160 /* Return if already the state */
161 if (REG_GET(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, 5, 4) == val)
162 return 0;
163
164 /* Command for power control of HDMI PHY */
165 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6);
166
167 /* Status of the power control of HDMI PHY */
168 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data),
169 HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
170 pr_err("Failed to set PHY power mode to %d\n", val);
171 return -ETIMEDOUT;
172 }
173
174 return 0;
175 }
176
177 /* PLL_PWR_CMD */
hdmi_set_pll_pwr(struct hdmi_ip_data * ip_data,enum hdmi_pll_pwr val)178 static int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val)
179 {
180 /* Command for power control of HDMI PLL */
181 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2);
182
183 /* wait till PHY_PWR_STATUS is set */
184 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL,
185 1, 0, val) != val) {
186 pr_err("Failed to set PLL_PWR_STATUS\n");
187 return -ETIMEDOUT;
188 }
189
190 return 0;
191 }
192
hdmi_pll_reset(struct hdmi_ip_data * ip_data)193 static int hdmi_pll_reset(struct hdmi_ip_data *ip_data)
194 {
195 /* SYSRESET controlled by power FSM */
196 REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
197
198 /* READ 0x0 reset is in progress */
199 if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data),
200 PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
201 pr_err("Failed to sysreset PLL\n");
202 return -ETIMEDOUT;
203 }
204
205 return 0;
206 }
207
ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data * ip_data)208 int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data)
209 {
210 u16 r = 0;
211
212 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
213 if (r)
214 return r;
215
216 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
217 if (r)
218 return r;
219
220 r = hdmi_pll_reset(ip_data);
221 if (r)
222 return r;
223
224 r = hdmi_pll_init(ip_data);
225 if (r)
226 return r;
227
228 return 0;
229 }
230
ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data * ip_data)231 void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data)
232 {
233 hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
234 }
235
hdmi_check_hpd_state(struct hdmi_ip_data * ip_data)236 static int hdmi_check_hpd_state(struct hdmi_ip_data *ip_data)
237 {
238 bool hpd;
239 int r;
240
241 mutex_lock(&ip_data->lock);
242
243 hpd = gpio_get_value(ip_data->hpd_gpio);
244
245 if (hpd)
246 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON);
247 else
248 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
249
250 if (r) {
251 DSSERR("Failed to %s PHY TX power\n",
252 hpd ? "enable" : "disable");
253 goto err;
254 }
255
256 err:
257 mutex_unlock(&ip_data->lock);
258 return r;
259 }
260
hpd_irq_handler(int irq,void * data)261 static irqreturn_t hpd_irq_handler(int irq, void *data)
262 {
263 struct hdmi_ip_data *ip_data = data;
264
265 hdmi_check_hpd_state(ip_data);
266
267 return IRQ_HANDLED;
268 }
269
ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data * ip_data)270 int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data)
271 {
272 u16 r = 0;
273 void __iomem *phy_base = hdmi_phy_base(ip_data);
274
275 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
276 if (r)
277 return r;
278
279 /*
280 * Read address 0 in order to get the SCP reset done completed
281 * Dummy access performed to make sure reset is done
282 */
283 hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL);
284
285 /*
286 * Write to phy address 0 to configure the clock
287 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
288 */
289 REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
290
291 /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
292 hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
293
294 /* Setup max LDO voltage */
295 REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
296
297 /* Write to phy address 3 to change the polarity control */
298 REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
299
300 r = request_threaded_irq(gpio_to_irq(ip_data->hpd_gpio),
301 NULL, hpd_irq_handler,
302 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
303 IRQF_ONESHOT, "hpd", ip_data);
304 if (r) {
305 DSSERR("HPD IRQ request failed\n");
306 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
307 return r;
308 }
309
310 r = hdmi_check_hpd_state(ip_data);
311 if (r) {
312 free_irq(gpio_to_irq(ip_data->hpd_gpio), ip_data);
313 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
314 return r;
315 }
316
317 return 0;
318 }
319
ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data * ip_data)320 void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data)
321 {
322 free_irq(gpio_to_irq(ip_data->hpd_gpio), ip_data);
323
324 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
325 }
326
hdmi_core_ddc_init(struct hdmi_ip_data * ip_data)327 static int hdmi_core_ddc_init(struct hdmi_ip_data *ip_data)
328 {
329 void __iomem *base = hdmi_core_sys_base(ip_data);
330
331 /* Turn on CLK for DDC */
332 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0);
333
334 /* IN_PROG */
335 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) {
336 /* Abort transaction */
337 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0);
338 /* IN_PROG */
339 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
340 4, 4, 0) != 0) {
341 DSSERR("Timeout aborting DDC transaction\n");
342 return -ETIMEDOUT;
343 }
344 }
345
346 /* Clk SCL Devices */
347 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
348
349 /* HDMI_CORE_DDC_STATUS_IN_PROG */
350 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
351 4, 4, 0) != 0) {
352 DSSERR("Timeout starting SCL clock\n");
353 return -ETIMEDOUT;
354 }
355
356 /* Clear FIFO */
357 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
358
359 /* HDMI_CORE_DDC_STATUS_IN_PROG */
360 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
361 4, 4, 0) != 0) {
362 DSSERR("Timeout clearing DDC fifo\n");
363 return -ETIMEDOUT;
364 }
365
366 return 0;
367 }
368
hdmi_core_ddc_edid(struct hdmi_ip_data * ip_data,u8 * pedid,int ext)369 static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data,
370 u8 *pedid, int ext)
371 {
372 void __iomem *base = hdmi_core_sys_base(ip_data);
373 u32 i;
374 char checksum;
375 u32 offset = 0;
376
377 /* HDMI_CORE_DDC_STATUS_IN_PROG */
378 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
379 4, 4, 0) != 0) {
380 DSSERR("Timeout waiting DDC to be ready\n");
381 return -ETIMEDOUT;
382 }
383
384 if (ext % 2 != 0)
385 offset = 0x80;
386
387 /* Load Segment Address Register */
388 REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0);
389
390 /* Load Slave Address Register */
391 REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
392
393 /* Load Offset Address Register */
394 REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
395
396 /* Load Byte Count */
397 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
398 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
399
400 /* Set DDC_CMD */
401 if (ext)
402 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
403 else
404 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
405
406 /* HDMI_CORE_DDC_STATUS_BUS_LOW */
407 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
408 pr_err("I2C Bus Low?\n");
409 return -EIO;
410 }
411 /* HDMI_CORE_DDC_STATUS_NO_ACK */
412 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
413 pr_err("I2C No Ack\n");
414 return -EIO;
415 }
416
417 for (i = 0; i < 0x80; ++i) {
418 int t;
419
420 /* IN_PROG */
421 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) {
422 DSSERR("operation stopped when reading edid\n");
423 return -EIO;
424 }
425
426 t = 0;
427 /* FIFO_EMPTY */
428 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) {
429 if (t++ > 10000) {
430 DSSERR("timeout reading edid\n");
431 return -ETIMEDOUT;
432 }
433 udelay(1);
434 }
435
436 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
437 }
438
439 checksum = 0;
440 for (i = 0; i < 0x80; ++i)
441 checksum += pedid[i];
442
443 if (checksum != 0) {
444 pr_err("E-EDID checksum failed!!\n");
445 return -EIO;
446 }
447
448 return 0;
449 }
450
ti_hdmi_4xxx_read_edid(struct hdmi_ip_data * ip_data,u8 * edid,int len)451 int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data,
452 u8 *edid, int len)
453 {
454 int r, l;
455
456 if (len < 128)
457 return -EINVAL;
458
459 r = hdmi_core_ddc_init(ip_data);
460 if (r)
461 return r;
462
463 r = hdmi_core_ddc_edid(ip_data, edid, 0);
464 if (r)
465 return r;
466
467 l = 128;
468
469 if (len >= 128 * 2 && edid[0x7e] > 0) {
470 r = hdmi_core_ddc_edid(ip_data, edid + 0x80, 1);
471 if (r)
472 return r;
473 l += 128;
474 }
475
476 return l;
477 }
478
ti_hdmi_4xxx_detect(struct hdmi_ip_data * ip_data)479 bool ti_hdmi_4xxx_detect(struct hdmi_ip_data *ip_data)
480 {
481 return gpio_get_value(ip_data->hpd_gpio);
482 }
483
hdmi_core_init(struct hdmi_core_video_config * video_cfg,struct hdmi_core_infoframe_avi * avi_cfg,struct hdmi_core_packet_enable_repeat * repeat_cfg)484 static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
485 struct hdmi_core_infoframe_avi *avi_cfg,
486 struct hdmi_core_packet_enable_repeat *repeat_cfg)
487 {
488 pr_debug("Enter hdmi_core_init\n");
489
490 /* video core */
491 video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
492 video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
493 video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
494 video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
495 video_cfg->hdmi_dvi = HDMI_DVI;
496 video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
497
498 /* info frame */
499 avi_cfg->db1_format = 0;
500 avi_cfg->db1_active_info = 0;
501 avi_cfg->db1_bar_info_dv = 0;
502 avi_cfg->db1_scan_info = 0;
503 avi_cfg->db2_colorimetry = 0;
504 avi_cfg->db2_aspect_ratio = 0;
505 avi_cfg->db2_active_fmt_ar = 0;
506 avi_cfg->db3_itc = 0;
507 avi_cfg->db3_ec = 0;
508 avi_cfg->db3_q_range = 0;
509 avi_cfg->db3_nup_scaling = 0;
510 avi_cfg->db4_videocode = 0;
511 avi_cfg->db5_pixel_repeat = 0;
512 avi_cfg->db6_7_line_eoftop = 0 ;
513 avi_cfg->db8_9_line_sofbottom = 0;
514 avi_cfg->db10_11_pixel_eofleft = 0;
515 avi_cfg->db12_13_pixel_sofright = 0;
516
517 /* packet enable and repeat */
518 repeat_cfg->audio_pkt = 0;
519 repeat_cfg->audio_pkt_repeat = 0;
520 repeat_cfg->avi_infoframe = 0;
521 repeat_cfg->avi_infoframe_repeat = 0;
522 repeat_cfg->gen_cntrl_pkt = 0;
523 repeat_cfg->gen_cntrl_pkt_repeat = 0;
524 repeat_cfg->generic_pkt = 0;
525 repeat_cfg->generic_pkt_repeat = 0;
526 }
527
hdmi_core_powerdown_disable(struct hdmi_ip_data * ip_data)528 static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data)
529 {
530 pr_debug("Enter hdmi_core_powerdown_disable\n");
531 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0);
532 }
533
hdmi_core_swreset_release(struct hdmi_ip_data * ip_data)534 static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data)
535 {
536 pr_debug("Enter hdmi_core_swreset_release\n");
537 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0);
538 }
539
hdmi_core_swreset_assert(struct hdmi_ip_data * ip_data)540 static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data)
541 {
542 pr_debug("Enter hdmi_core_swreset_assert\n");
543 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0);
544 }
545
546 /* HDMI_CORE_VIDEO_CONFIG */
hdmi_core_video_config(struct hdmi_ip_data * ip_data,struct hdmi_core_video_config * cfg)547 static void hdmi_core_video_config(struct hdmi_ip_data *ip_data,
548 struct hdmi_core_video_config *cfg)
549 {
550 u32 r = 0;
551 void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
552
553 /* sys_ctrl1 default configuration not tunable */
554 r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1);
555 r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
556 r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
557 r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
558 r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
559 hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r);
560
561 REG_FLD_MOD(core_sys_base,
562 HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
563
564 /* Vid_Mode */
565 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
566
567 /* dither truncation configuration */
568 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
569 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
570 r = FLD_MOD(r, 1, 5, 5);
571 } else {
572 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
573 r = FLD_MOD(r, 0, 5, 5);
574 }
575 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
576
577 /* HDMI_Ctrl */
578 r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL);
579 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
580 r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
581 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
582 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r);
583
584 /* TMDS_CTRL */
585 REG_FLD_MOD(core_sys_base,
586 HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
587 }
588
hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data * ip_data)589 static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data)
590 {
591 u32 val;
592 char sum = 0, checksum = 0;
593 void __iomem *av_base = hdmi_av_base(ip_data);
594 struct hdmi_core_infoframe_avi info_avi = ip_data->avi_cfg;
595
596 sum += 0x82 + 0x002 + 0x00D;
597 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
598 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002);
599 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D);
600
601 val = (info_avi.db1_format << 5) |
602 (info_avi.db1_active_info << 4) |
603 (info_avi.db1_bar_info_dv << 2) |
604 (info_avi.db1_scan_info);
605 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val);
606 sum += val;
607
608 val = (info_avi.db2_colorimetry << 6) |
609 (info_avi.db2_aspect_ratio << 4) |
610 (info_avi.db2_active_fmt_ar);
611 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val);
612 sum += val;
613
614 val = (info_avi.db3_itc << 7) |
615 (info_avi.db3_ec << 4) |
616 (info_avi.db3_q_range << 2) |
617 (info_avi.db3_nup_scaling);
618 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val);
619 sum += val;
620
621 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3),
622 info_avi.db4_videocode);
623 sum += info_avi.db4_videocode;
624
625 val = info_avi.db5_pixel_repeat;
626 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val);
627 sum += val;
628
629 val = info_avi.db6_7_line_eoftop & 0x00FF;
630 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val);
631 sum += val;
632
633 val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
634 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val);
635 sum += val;
636
637 val = info_avi.db8_9_line_sofbottom & 0x00FF;
638 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val);
639 sum += val;
640
641 val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
642 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val);
643 sum += val;
644
645 val = info_avi.db10_11_pixel_eofleft & 0x00FF;
646 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val);
647 sum += val;
648
649 val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
650 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val);
651 sum += val;
652
653 val = info_avi.db12_13_pixel_sofright & 0x00FF;
654 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val);
655 sum += val;
656
657 val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
658 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val);
659 sum += val;
660
661 checksum = 0x100 - sum;
662 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum);
663 }
664
hdmi_core_av_packet_config(struct hdmi_ip_data * ip_data,struct hdmi_core_packet_enable_repeat repeat_cfg)665 static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data,
666 struct hdmi_core_packet_enable_repeat repeat_cfg)
667 {
668 /* enable/repeat the infoframe */
669 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1,
670 (repeat_cfg.audio_pkt << 5) |
671 (repeat_cfg.audio_pkt_repeat << 4) |
672 (repeat_cfg.avi_infoframe << 1) |
673 (repeat_cfg.avi_infoframe_repeat));
674
675 /* enable/repeat the packet */
676 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2,
677 (repeat_cfg.gen_cntrl_pkt << 3) |
678 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
679 (repeat_cfg.generic_pkt << 1) |
680 (repeat_cfg.generic_pkt_repeat));
681 }
682
hdmi_wp_init(struct omap_video_timings * timings,struct hdmi_video_format * video_fmt)683 static void hdmi_wp_init(struct omap_video_timings *timings,
684 struct hdmi_video_format *video_fmt)
685 {
686 pr_debug("Enter hdmi_wp_init\n");
687
688 timings->hbp = 0;
689 timings->hfp = 0;
690 timings->hsw = 0;
691 timings->vbp = 0;
692 timings->vfp = 0;
693 timings->vsw = 0;
694
695 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
696 video_fmt->y_res = 0;
697 video_fmt->x_res = 0;
698
699 }
700
ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data * ip_data)701 int ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data)
702 {
703 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, true, 31, 31);
704 return 0;
705 }
706
ti_hdmi_4xxx_wp_video_stop(struct hdmi_ip_data * ip_data)707 void ti_hdmi_4xxx_wp_video_stop(struct hdmi_ip_data *ip_data)
708 {
709 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, false, 31, 31);
710 }
711
hdmi_wp_video_init_format(struct hdmi_video_format * video_fmt,struct omap_video_timings * timings,struct hdmi_config * param)712 static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
713 struct omap_video_timings *timings, struct hdmi_config *param)
714 {
715 pr_debug("Enter hdmi_wp_video_init_format\n");
716
717 video_fmt->y_res = param->timings.y_res;
718 video_fmt->x_res = param->timings.x_res;
719
720 timings->hbp = param->timings.hbp;
721 timings->hfp = param->timings.hfp;
722 timings->hsw = param->timings.hsw;
723 timings->vbp = param->timings.vbp;
724 timings->vfp = param->timings.vfp;
725 timings->vsw = param->timings.vsw;
726 }
727
hdmi_wp_video_config_format(struct hdmi_ip_data * ip_data,struct hdmi_video_format * video_fmt)728 static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
729 struct hdmi_video_format *video_fmt)
730 {
731 u32 l = 0;
732
733 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG,
734 video_fmt->packing_mode, 10, 8);
735
736 l |= FLD_VAL(video_fmt->y_res, 31, 16);
737 l |= FLD_VAL(video_fmt->x_res, 15, 0);
738 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l);
739 }
740
hdmi_wp_video_config_interface(struct hdmi_ip_data * ip_data)741 static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data)
742 {
743 u32 r;
744 bool vsync_pol, hsync_pol;
745 pr_debug("Enter hdmi_wp_video_config_interface\n");
746
747 vsync_pol = ip_data->cfg.timings.vsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
748 hsync_pol = ip_data->cfg.timings.hsync_level == OMAPDSS_SIG_ACTIVE_HIGH;
749
750 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
751 r = FLD_MOD(r, vsync_pol, 7, 7);
752 r = FLD_MOD(r, hsync_pol, 6, 6);
753 r = FLD_MOD(r, ip_data->cfg.timings.interlace, 3, 3);
754 r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
755 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
756 }
757
hdmi_wp_video_config_timing(struct hdmi_ip_data * ip_data,struct omap_video_timings * timings)758 static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data,
759 struct omap_video_timings *timings)
760 {
761 u32 timing_h = 0;
762 u32 timing_v = 0;
763
764 pr_debug("Enter hdmi_wp_video_config_timing\n");
765
766 timing_h |= FLD_VAL(timings->hbp, 31, 20);
767 timing_h |= FLD_VAL(timings->hfp, 19, 8);
768 timing_h |= FLD_VAL(timings->hsw, 7, 0);
769 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h);
770
771 timing_v |= FLD_VAL(timings->vbp, 31, 20);
772 timing_v |= FLD_VAL(timings->vfp, 19, 8);
773 timing_v |= FLD_VAL(timings->vsw, 7, 0);
774 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
775 }
776
ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data * ip_data)777 void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data)
778 {
779 /* HDMI */
780 struct omap_video_timings video_timing;
781 struct hdmi_video_format video_format;
782 /* HDMI core */
783 struct hdmi_core_infoframe_avi avi_cfg = ip_data->avi_cfg;
784 struct hdmi_core_video_config v_core_cfg;
785 struct hdmi_core_packet_enable_repeat repeat_cfg;
786 struct hdmi_config *cfg = &ip_data->cfg;
787
788 hdmi_wp_init(&video_timing, &video_format);
789
790 hdmi_core_init(&v_core_cfg,
791 &avi_cfg,
792 &repeat_cfg);
793
794 hdmi_wp_video_init_format(&video_format, &video_timing, cfg);
795
796 hdmi_wp_video_config_timing(ip_data, &video_timing);
797
798 /* video config */
799 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
800
801 hdmi_wp_video_config_format(ip_data, &video_format);
802
803 hdmi_wp_video_config_interface(ip_data);
804
805 /*
806 * configure core video part
807 * set software reset in the core
808 */
809 hdmi_core_swreset_assert(ip_data);
810
811 /* power down off */
812 hdmi_core_powerdown_disable(ip_data);
813
814 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
815 v_core_cfg.hdmi_dvi = cfg->cm.mode;
816
817 hdmi_core_video_config(ip_data, &v_core_cfg);
818
819 /* release software reset in the core */
820 hdmi_core_swreset_release(ip_data);
821
822 /*
823 * configure packet
824 * info frame video see doc CEA861-D page 65
825 */
826 avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
827 avi_cfg.db1_active_info =
828 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
829 avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
830 avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
831 avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
832 avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
833 avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
834 avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
835 avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
836 avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
837 avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
838 avi_cfg.db4_videocode = cfg->cm.code;
839 avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
840 avi_cfg.db6_7_line_eoftop = 0;
841 avi_cfg.db8_9_line_sofbottom = 0;
842 avi_cfg.db10_11_pixel_eofleft = 0;
843 avi_cfg.db12_13_pixel_sofright = 0;
844
845 hdmi_core_aux_infoframe_avi_config(ip_data);
846
847 /* enable/repeat the infoframe */
848 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
849 repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
850 /* wakeup */
851 repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
852 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
853 hdmi_core_av_packet_config(ip_data, repeat_cfg);
854 }
855
ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data * ip_data,struct seq_file * s)856 void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
857 {
858 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r,\
859 hdmi_read_reg(hdmi_wp_base(ip_data), r))
860
861 DUMPREG(HDMI_WP_REVISION);
862 DUMPREG(HDMI_WP_SYSCONFIG);
863 DUMPREG(HDMI_WP_IRQSTATUS_RAW);
864 DUMPREG(HDMI_WP_IRQSTATUS);
865 DUMPREG(HDMI_WP_PWR_CTRL);
866 DUMPREG(HDMI_WP_IRQENABLE_SET);
867 DUMPREG(HDMI_WP_VIDEO_CFG);
868 DUMPREG(HDMI_WP_VIDEO_SIZE);
869 DUMPREG(HDMI_WP_VIDEO_TIMING_H);
870 DUMPREG(HDMI_WP_VIDEO_TIMING_V);
871 DUMPREG(HDMI_WP_WP_CLK);
872 DUMPREG(HDMI_WP_AUDIO_CFG);
873 DUMPREG(HDMI_WP_AUDIO_CFG2);
874 DUMPREG(HDMI_WP_AUDIO_CTRL);
875 DUMPREG(HDMI_WP_AUDIO_DATA);
876 }
877
ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data * ip_data,struct seq_file * s)878 void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
879 {
880 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
881 hdmi_read_reg(hdmi_pll_base(ip_data), r))
882
883 DUMPPLL(PLLCTRL_PLL_CONTROL);
884 DUMPPLL(PLLCTRL_PLL_STATUS);
885 DUMPPLL(PLLCTRL_PLL_GO);
886 DUMPPLL(PLLCTRL_CFG1);
887 DUMPPLL(PLLCTRL_CFG2);
888 DUMPPLL(PLLCTRL_CFG3);
889 DUMPPLL(PLLCTRL_CFG4);
890 }
891
ti_hdmi_4xxx_core_dump(struct hdmi_ip_data * ip_data,struct seq_file * s)892 void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
893 {
894 int i;
895
896 #define CORE_REG(i, name) name(i)
897 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
898 hdmi_read_reg(hdmi_core_sys_base(ip_data), r))
899 #define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\
900 hdmi_read_reg(hdmi_av_base(ip_data), r))
901 #define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \
902 (i < 10) ? 32 - (int)strlen(#r) : 31 - (int)strlen(#r), " ", \
903 hdmi_read_reg(hdmi_av_base(ip_data), CORE_REG(i, r)))
904
905 DUMPCORE(HDMI_CORE_SYS_VND_IDL);
906 DUMPCORE(HDMI_CORE_SYS_DEV_IDL);
907 DUMPCORE(HDMI_CORE_SYS_DEV_IDH);
908 DUMPCORE(HDMI_CORE_SYS_DEV_REV);
909 DUMPCORE(HDMI_CORE_SYS_SRST);
910 DUMPCORE(HDMI_CORE_CTRL1);
911 DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
912 DUMPCORE(HDMI_CORE_SYS_DE_DLY);
913 DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
914 DUMPCORE(HDMI_CORE_SYS_DE_TOP);
915 DUMPCORE(HDMI_CORE_SYS_DE_CNTL);
916 DUMPCORE(HDMI_CORE_SYS_DE_CNTH);
917 DUMPCORE(HDMI_CORE_SYS_DE_LINL);
918 DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);
919 DUMPCORE(HDMI_CORE_SYS_VID_ACEN);
920 DUMPCORE(HDMI_CORE_SYS_VID_MODE);
921 DUMPCORE(HDMI_CORE_SYS_INTR_STATE);
922 DUMPCORE(HDMI_CORE_SYS_INTR1);
923 DUMPCORE(HDMI_CORE_SYS_INTR2);
924 DUMPCORE(HDMI_CORE_SYS_INTR3);
925 DUMPCORE(HDMI_CORE_SYS_INTR4);
926 DUMPCORE(HDMI_CORE_SYS_UMASK1);
927 DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);
928
929 DUMPCORE(HDMI_CORE_DDC_ADDR);
930 DUMPCORE(HDMI_CORE_DDC_SEGM);
931 DUMPCORE(HDMI_CORE_DDC_OFFSET);
932 DUMPCORE(HDMI_CORE_DDC_COUNT1);
933 DUMPCORE(HDMI_CORE_DDC_COUNT2);
934 DUMPCORE(HDMI_CORE_DDC_STATUS);
935 DUMPCORE(HDMI_CORE_DDC_CMD);
936 DUMPCORE(HDMI_CORE_DDC_DATA);
937
938 DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL);
939 DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL);
940 DUMPCOREAV(HDMI_CORE_AV_N_SVAL1);
941 DUMPCOREAV(HDMI_CORE_AV_N_SVAL2);
942 DUMPCOREAV(HDMI_CORE_AV_N_SVAL3);
943 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL1);
944 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL2);
945 DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL3);
946 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL1);
947 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL2);
948 DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL3);
949 DUMPCOREAV(HDMI_CORE_AV_AUD_MODE);
950 DUMPCOREAV(HDMI_CORE_AV_SPDIF_CTRL);
951 DUMPCOREAV(HDMI_CORE_AV_HW_SPDIF_FS);
952 DUMPCOREAV(HDMI_CORE_AV_SWAP_I2S);
953 DUMPCOREAV(HDMI_CORE_AV_SPDIF_ERTH);
954 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_MAP);
955 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_CTRL);
956 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST0);
957 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST1);
958 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST2);
959 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST4);
960 DUMPCOREAV(HDMI_CORE_AV_I2S_CHST5);
961 DUMPCOREAV(HDMI_CORE_AV_ASRC);
962 DUMPCOREAV(HDMI_CORE_AV_I2S_IN_LEN);
963 DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL);
964 DUMPCOREAV(HDMI_CORE_AV_AUDO_TXSTAT);
965 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_1);
966 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_2);
967 DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_3);
968 DUMPCOREAV(HDMI_CORE_AV_TEST_TXCTRL);
969 DUMPCOREAV(HDMI_CORE_AV_DPD);
970 DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1);
971 DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2);
972 DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE);
973 DUMPCOREAV(HDMI_CORE_AV_AVI_VERS);
974 DUMPCOREAV(HDMI_CORE_AV_AVI_LEN);
975 DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM);
976
977 for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++)
978 DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE);
979
980 DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE);
981 DUMPCOREAV(HDMI_CORE_AV_SPD_VERS);
982 DUMPCOREAV(HDMI_CORE_AV_SPD_LEN);
983 DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM);
984
985 for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++)
986 DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE);
987
988 DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE);
989 DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS);
990 DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN);
991 DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM);
992
993 for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++)
994 DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE);
995
996 DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE);
997 DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS);
998 DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN);
999 DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM);
1000
1001 for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++)
1002 DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE);
1003
1004 for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++)
1005 DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE);
1006
1007 DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1);
1008
1009 for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++)
1010 DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE);
1011
1012 DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID);
1013 }
1014
ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data * ip_data,struct seq_file * s)1015 void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
1016 {
1017 #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
1018 hdmi_read_reg(hdmi_phy_base(ip_data), r))
1019
1020 DUMPPHY(HDMI_TXPHY_TX_CTRL);
1021 DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
1022 DUMPPHY(HDMI_TXPHY_POWER_CTRL);
1023 DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
1024 }
1025
1026 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
ti_hdmi_4xxx_wp_audio_config_format(struct hdmi_ip_data * ip_data,struct hdmi_audio_format * aud_fmt)1027 static void ti_hdmi_4xxx_wp_audio_config_format(struct hdmi_ip_data *ip_data,
1028 struct hdmi_audio_format *aud_fmt)
1029 {
1030 u32 r;
1031
1032 DSSDBG("Enter hdmi_wp_audio_config_format\n");
1033
1034 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG);
1035 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
1036 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
1037 r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
1038 r = FLD_MOD(r, aud_fmt->type, 4, 4);
1039 r = FLD_MOD(r, aud_fmt->justification, 3, 3);
1040 r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
1041 r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
1042 r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
1043 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG, r);
1044 }
1045
ti_hdmi_4xxx_wp_audio_config_dma(struct hdmi_ip_data * ip_data,struct hdmi_audio_dma * aud_dma)1046 static void ti_hdmi_4xxx_wp_audio_config_dma(struct hdmi_ip_data *ip_data,
1047 struct hdmi_audio_dma *aud_dma)
1048 {
1049 u32 r;
1050
1051 DSSDBG("Enter hdmi_wp_audio_config_dma\n");
1052
1053 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2);
1054 r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
1055 r = FLD_MOD(r, aud_dma->block_size, 7, 0);
1056 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2, r);
1057
1058 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL);
1059 r = FLD_MOD(r, aud_dma->mode, 9, 9);
1060 r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
1061 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL, r);
1062 }
1063
ti_hdmi_4xxx_core_audio_config(struct hdmi_ip_data * ip_data,struct hdmi_core_audio_config * cfg)1064 static void ti_hdmi_4xxx_core_audio_config(struct hdmi_ip_data *ip_data,
1065 struct hdmi_core_audio_config *cfg)
1066 {
1067 u32 r;
1068 void __iomem *av_base = hdmi_av_base(ip_data);
1069
1070 /*
1071 * Parameters for generation of Audio Clock Recovery packets
1072 */
1073 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
1074 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
1075 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
1076
1077 if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
1078 REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
1079 REG_FLD_MOD(av_base,
1080 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
1081 REG_FLD_MOD(av_base,
1082 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
1083 } else {
1084 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
1085 cfg->aud_par_busclk, 7, 0);
1086 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
1087 (cfg->aud_par_busclk >> 8), 7, 0);
1088 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
1089 (cfg->aud_par_busclk >> 16), 7, 0);
1090 }
1091
1092 /* Set ACR clock divisor */
1093 REG_FLD_MOD(av_base,
1094 HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
1095
1096 r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
1097 /*
1098 * Use TMDS clock for ACR packets. For devices that use
1099 * the MCLK, this is the first part of the MCLK initialization.
1100 */
1101 r = FLD_MOD(r, 0, 2, 2);
1102
1103 r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
1104 r = FLD_MOD(r, cfg->cts_mode, 0, 0);
1105 hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
1106
1107 /* For devices using MCLK, this completes its initialization. */
1108 if (cfg->use_mclk)
1109 REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2);
1110
1111 /* Override of SPDIF sample frequency with value in I2S_CHST4 */
1112 REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
1113 cfg->fs_override, 1, 1);
1114
1115 /*
1116 * Set IEC-60958-3 channel status word. It is passed to the IP
1117 * just as it is received. The user of the driver is responsible
1118 * for its contents.
1119 */
1120 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST0,
1121 cfg->iec60958_cfg->status[0]);
1122 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST1,
1123 cfg->iec60958_cfg->status[1]);
1124 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST2,
1125 cfg->iec60958_cfg->status[2]);
1126 /* yes, this is correct: status[3] goes to CHST4 register */
1127 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST4,
1128 cfg->iec60958_cfg->status[3]);
1129 /* yes, this is correct: status[4] goes to CHST5 register */
1130 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5,
1131 cfg->iec60958_cfg->status[4]);
1132
1133 /* set I2S parameters */
1134 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
1135 r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
1136 r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
1137 r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
1138 r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
1139 r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
1140 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r);
1141
1142 REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN,
1143 cfg->i2s_cfg.in_length_bits, 3, 0);
1144
1145 /* Audio channels and mode parameters */
1146 REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
1147 r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
1148 r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
1149 r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
1150 r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
1151 r = FLD_MOD(r, cfg->en_spdif, 1, 1);
1152 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r);
1153
1154 /* Audio channel mappings */
1155 /* TODO: Make channel mapping dynamic. For now, map channels
1156 * in the ALSA order: FL/FR/RL/RR/C/LFE/SL/SR. Remapping is needed as
1157 * HDMI speaker order is different. See CEA-861 Section 6.6.2.
1158 */
1159 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_MAP, 0x78);
1160 REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5);
1161 }
1162
ti_hdmi_4xxx_core_audio_infoframe_cfg(struct hdmi_ip_data * ip_data,struct snd_cea_861_aud_if * info_aud)1163 static void ti_hdmi_4xxx_core_audio_infoframe_cfg(struct hdmi_ip_data *ip_data,
1164 struct snd_cea_861_aud_if *info_aud)
1165 {
1166 u8 sum = 0, checksum = 0;
1167 void __iomem *av_base = hdmi_av_base(ip_data);
1168
1169 /*
1170 * Set audio info frame type, version and length as
1171 * described in HDMI 1.4a Section 8.2.2 specification.
1172 * Checksum calculation is defined in Section 5.3.5.
1173 */
1174 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84);
1175 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01);
1176 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a);
1177 sum += 0x84 + 0x001 + 0x00a;
1178
1179 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0),
1180 info_aud->db1_ct_cc);
1181 sum += info_aud->db1_ct_cc;
1182
1183 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1),
1184 info_aud->db2_sf_ss);
1185 sum += info_aud->db2_sf_ss;
1186
1187 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3);
1188 sum += info_aud->db3;
1189
1190 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca);
1191 sum += info_aud->db4_ca;
1192
1193 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4),
1194 info_aud->db5_dminh_lsv);
1195 sum += info_aud->db5_dminh_lsv;
1196
1197 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
1198 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
1199 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
1200 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
1201 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
1202
1203 checksum = 0x100 - sum;
1204 hdmi_write_reg(av_base,
1205 HDMI_CORE_AV_AUDIO_CHSUM, checksum);
1206
1207 /*
1208 * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
1209 * is available.
1210 */
1211 }
1212
ti_hdmi_4xxx_audio_config(struct hdmi_ip_data * ip_data,struct omap_dss_audio * audio)1213 int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data,
1214 struct omap_dss_audio *audio)
1215 {
1216 struct hdmi_audio_format audio_format;
1217 struct hdmi_audio_dma audio_dma;
1218 struct hdmi_core_audio_config core;
1219 int err, n, cts, channel_count;
1220 unsigned int fs_nr;
1221 bool word_length_16b = false;
1222
1223 if (!audio || !audio->iec || !audio->cea || !ip_data)
1224 return -EINVAL;
1225
1226 core.iec60958_cfg = audio->iec;
1227 /*
1228 * In the IEC-60958 status word, check if the audio sample word length
1229 * is 16-bit as several optimizations can be performed in such case.
1230 */
1231 if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24))
1232 if (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16)
1233 word_length_16b = true;
1234
1235 /* I2S configuration. See Phillips' specification */
1236 if (word_length_16b)
1237 core.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
1238 else
1239 core.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
1240 /*
1241 * The I2S input word length is twice the lenght given in the IEC-60958
1242 * status word. If the word size is greater than
1243 * 20 bits, increment by one.
1244 */
1245 core.i2s_cfg.in_length_bits = audio->iec->status[4]
1246 & IEC958_AES4_CON_WORDLEN;
1247 if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24)
1248 core.i2s_cfg.in_length_bits++;
1249 core.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
1250 core.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
1251 core.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
1252 core.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
1253
1254 /* convert sample frequency to a number */
1255 switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
1256 case IEC958_AES3_CON_FS_32000:
1257 fs_nr = 32000;
1258 break;
1259 case IEC958_AES3_CON_FS_44100:
1260 fs_nr = 44100;
1261 break;
1262 case IEC958_AES3_CON_FS_48000:
1263 fs_nr = 48000;
1264 break;
1265 case IEC958_AES3_CON_FS_88200:
1266 fs_nr = 88200;
1267 break;
1268 case IEC958_AES3_CON_FS_96000:
1269 fs_nr = 96000;
1270 break;
1271 case IEC958_AES3_CON_FS_176400:
1272 fs_nr = 176400;
1273 break;
1274 case IEC958_AES3_CON_FS_192000:
1275 fs_nr = 192000;
1276 break;
1277 default:
1278 return -EINVAL;
1279 }
1280
1281 err = hdmi_compute_acr(fs_nr, &n, &cts);
1282
1283 /* Audio clock regeneration settings */
1284 core.n = n;
1285 core.cts = cts;
1286 if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
1287 core.aud_par_busclk = 0;
1288 core.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
1289 core.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK);
1290 } else {
1291 core.aud_par_busclk = (((128 * 31) - 1) << 8);
1292 core.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
1293 core.use_mclk = true;
1294 }
1295
1296 if (core.use_mclk)
1297 core.mclk_mode = HDMI_AUDIO_MCLK_128FS;
1298
1299 /* Audio channels settings */
1300 channel_count = (audio->cea->db1_ct_cc &
1301 CEA861_AUDIO_INFOFRAME_DB1CC) + 1;
1302
1303 switch (channel_count) {
1304 case 2:
1305 audio_format.active_chnnls_msk = 0x03;
1306 break;
1307 case 3:
1308 audio_format.active_chnnls_msk = 0x07;
1309 break;
1310 case 4:
1311 audio_format.active_chnnls_msk = 0x0f;
1312 break;
1313 case 5:
1314 audio_format.active_chnnls_msk = 0x1f;
1315 break;
1316 case 6:
1317 audio_format.active_chnnls_msk = 0x3f;
1318 break;
1319 case 7:
1320 audio_format.active_chnnls_msk = 0x7f;
1321 break;
1322 case 8:
1323 audio_format.active_chnnls_msk = 0xff;
1324 break;
1325 default:
1326 return -EINVAL;
1327 }
1328
1329 /*
1330 * the HDMI IP needs to enable four stereo channels when transmitting
1331 * more than 2 audio channels
1332 */
1333 if (channel_count == 2) {
1334 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
1335 core.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
1336 core.layout = HDMI_AUDIO_LAYOUT_2CH;
1337 } else {
1338 audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS;
1339 core.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN |
1340 HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN |
1341 HDMI_AUDIO_I2S_SD3_EN;
1342 core.layout = HDMI_AUDIO_LAYOUT_8CH;
1343 }
1344
1345 core.en_spdif = false;
1346 /* use sample frequency from channel status word */
1347 core.fs_override = true;
1348 /* enable ACR packets */
1349 core.en_acr_pkt = true;
1350 /* disable direct streaming digital audio */
1351 core.en_dsd_audio = false;
1352 /* use parallel audio interface */
1353 core.en_parallel_aud_input = true;
1354
1355 /* DMA settings */
1356 if (word_length_16b)
1357 audio_dma.transfer_size = 0x10;
1358 else
1359 audio_dma.transfer_size = 0x20;
1360 audio_dma.block_size = 0xC0;
1361 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
1362 audio_dma.fifo_threshold = 0x20; /* in number of samples */
1363
1364 /* audio FIFO format settings */
1365 if (word_length_16b) {
1366 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
1367 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
1368 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
1369 } else {
1370 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
1371 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
1372 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
1373 }
1374 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
1375 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
1376 /* disable start/stop signals of IEC 60958 blocks */
1377 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
1378
1379 /* configure DMA and audio FIFO format*/
1380 ti_hdmi_4xxx_wp_audio_config_dma(ip_data, &audio_dma);
1381 ti_hdmi_4xxx_wp_audio_config_format(ip_data, &audio_format);
1382
1383 /* configure the core*/
1384 ti_hdmi_4xxx_core_audio_config(ip_data, &core);
1385
1386 /* configure CEA 861 audio infoframe*/
1387 ti_hdmi_4xxx_core_audio_infoframe_cfg(ip_data, audio->cea);
1388
1389 return 0;
1390 }
1391
ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data * ip_data)1392 int ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data)
1393 {
1394 REG_FLD_MOD(hdmi_wp_base(ip_data),
1395 HDMI_WP_AUDIO_CTRL, true, 31, 31);
1396 return 0;
1397 }
1398
ti_hdmi_4xxx_wp_audio_disable(struct hdmi_ip_data * ip_data)1399 void ti_hdmi_4xxx_wp_audio_disable(struct hdmi_ip_data *ip_data)
1400 {
1401 REG_FLD_MOD(hdmi_wp_base(ip_data),
1402 HDMI_WP_AUDIO_CTRL, false, 31, 31);
1403 }
1404
ti_hdmi_4xxx_audio_start(struct hdmi_ip_data * ip_data)1405 int ti_hdmi_4xxx_audio_start(struct hdmi_ip_data *ip_data)
1406 {
1407 REG_FLD_MOD(hdmi_av_base(ip_data),
1408 HDMI_CORE_AV_AUD_MODE, true, 0, 0);
1409 REG_FLD_MOD(hdmi_wp_base(ip_data),
1410 HDMI_WP_AUDIO_CTRL, true, 30, 30);
1411 return 0;
1412 }
1413
ti_hdmi_4xxx_audio_stop(struct hdmi_ip_data * ip_data)1414 void ti_hdmi_4xxx_audio_stop(struct hdmi_ip_data *ip_data)
1415 {
1416 REG_FLD_MOD(hdmi_av_base(ip_data),
1417 HDMI_CORE_AV_AUD_MODE, false, 0, 0);
1418 REG_FLD_MOD(hdmi_wp_base(ip_data),
1419 HDMI_WP_AUDIO_CTRL, false, 30, 30);
1420 }
1421
ti_hdmi_4xxx_audio_get_dma_port(u32 * offset,u32 * size)1422 int ti_hdmi_4xxx_audio_get_dma_port(u32 *offset, u32 *size)
1423 {
1424 if (!offset || !size)
1425 return -EINVAL;
1426 *offset = HDMI_WP_AUDIO_DATA;
1427 *size = 4;
1428 return 0;
1429 }
1430 #endif
1431