1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
9 *
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
14 */
15
16 enum fields {
17 RS = 0x001,
18 RT = 0x002,
19 RD = 0x004,
20 RE = 0x008,
21 SIMM = 0x010,
22 UIMM = 0x020,
23 BIMM = 0x040,
24 JIMM = 0x080,
25 FUNC = 0x100,
26 SET = 0x200,
27 SCIMM = 0x400,
28 SIMM9 = 0x800
29 };
30
31 #define OP_MASK 0x3f
32 #define OP_SH 26
33 #define RD_MASK 0x1f
34 #define RD_SH 11
35 #define RE_MASK 0x1f
36 #define RE_SH 6
37 #define IMM_MASK 0xffff
38 #define IMM_SH 0
39 #define JIMM_MASK 0x3ffffff
40 #define JIMM_SH 0
41 #define FUNC_MASK 0x3f
42 #define FUNC_SH 0
43 #define SET_MASK 0x7
44 #define SET_SH 0
45 #define SIMM9_SH 7
46 #define SIMM9_MASK 0x1ff
47
48 enum opcode {
49 insn_invalid,
50 insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
51 insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
52 insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
53 insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
54 insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
55 insn_ext, insn_ins, insn_j, insn_jal, insn_jr, insn_ld, insn_ldx,
56 insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0,
57 insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd,
58 insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
59 insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor,
60 insn_xori,
61 };
62
63 struct insn {
64 enum opcode opcode;
65 u32 match;
66 enum fields fields;
67 };
68
build_rs(u32 arg)69 static inline __uasminit u32 build_rs(u32 arg)
70 {
71 WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
72
73 return (arg & RS_MASK) << RS_SH;
74 }
75
build_rt(u32 arg)76 static inline __uasminit u32 build_rt(u32 arg)
77 {
78 WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
79
80 return (arg & RT_MASK) << RT_SH;
81 }
82
build_rd(u32 arg)83 static inline __uasminit u32 build_rd(u32 arg)
84 {
85 WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
86
87 return (arg & RD_MASK) << RD_SH;
88 }
89
build_re(u32 arg)90 static inline __uasminit u32 build_re(u32 arg)
91 {
92 WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
93
94 return (arg & RE_MASK) << RE_SH;
95 }
96
build_simm(s32 arg)97 static inline __uasminit u32 build_simm(s32 arg)
98 {
99 WARN(arg > 0x7fff || arg < -0x8000,
100 KERN_WARNING "Micro-assembler field overflow\n");
101
102 return arg & 0xffff;
103 }
104
build_uimm(u32 arg)105 static inline __uasminit u32 build_uimm(u32 arg)
106 {
107 WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
108
109 return arg & IMM_MASK;
110 }
111
build_scimm(u32 arg)112 static inline __uasminit u32 build_scimm(u32 arg)
113 {
114 WARN(arg & ~SCIMM_MASK,
115 KERN_WARNING "Micro-assembler field overflow\n");
116
117 return (arg & SCIMM_MASK) << SCIMM_SH;
118 }
119
build_func(u32 arg)120 static inline __uasminit u32 build_func(u32 arg)
121 {
122 WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
123
124 return arg & FUNC_MASK;
125 }
126
build_set(u32 arg)127 static inline __uasminit u32 build_set(u32 arg)
128 {
129 WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
130
131 return arg & SET_MASK;
132 }
133
134 static void __uasminit build_insn(u32 **buf, enum opcode opc, ...);
135
136 #define I_u1u2u3(op) \
137 Ip_u1u2u3(op) \
138 { \
139 build_insn(buf, insn##op, a, b, c); \
140 } \
141 UASM_EXPORT_SYMBOL(uasm_i##op);
142
143 #define I_u2u1u3(op) \
144 Ip_u2u1u3(op) \
145 { \
146 build_insn(buf, insn##op, b, a, c); \
147 } \
148 UASM_EXPORT_SYMBOL(uasm_i##op);
149
150 #define I_u3u1u2(op) \
151 Ip_u3u1u2(op) \
152 { \
153 build_insn(buf, insn##op, b, c, a); \
154 } \
155 UASM_EXPORT_SYMBOL(uasm_i##op);
156
157 #define I_u1u2s3(op) \
158 Ip_u1u2s3(op) \
159 { \
160 build_insn(buf, insn##op, a, b, c); \
161 } \
162 UASM_EXPORT_SYMBOL(uasm_i##op);
163
164 #define I_u2s3u1(op) \
165 Ip_u2s3u1(op) \
166 { \
167 build_insn(buf, insn##op, c, a, b); \
168 } \
169 UASM_EXPORT_SYMBOL(uasm_i##op);
170
171 #define I_u2u1s3(op) \
172 Ip_u2u1s3(op) \
173 { \
174 build_insn(buf, insn##op, b, a, c); \
175 } \
176 UASM_EXPORT_SYMBOL(uasm_i##op);
177
178 #define I_u2u1msbu3(op) \
179 Ip_u2u1msbu3(op) \
180 { \
181 build_insn(buf, insn##op, b, a, c+d-1, c); \
182 } \
183 UASM_EXPORT_SYMBOL(uasm_i##op);
184
185 #define I_u2u1msb32u3(op) \
186 Ip_u2u1msbu3(op) \
187 { \
188 build_insn(buf, insn##op, b, a, c+d-33, c); \
189 } \
190 UASM_EXPORT_SYMBOL(uasm_i##op);
191
192 #define I_u2u1msbdu3(op) \
193 Ip_u2u1msbu3(op) \
194 { \
195 build_insn(buf, insn##op, b, a, d-1, c); \
196 } \
197 UASM_EXPORT_SYMBOL(uasm_i##op);
198
199 #define I_u1u2(op) \
200 Ip_u1u2(op) \
201 { \
202 build_insn(buf, insn##op, a, b); \
203 } \
204 UASM_EXPORT_SYMBOL(uasm_i##op);
205
206 #define I_u1s2(op) \
207 Ip_u1s2(op) \
208 { \
209 build_insn(buf, insn##op, a, b); \
210 } \
211 UASM_EXPORT_SYMBOL(uasm_i##op);
212
213 #define I_u1(op) \
214 Ip_u1(op) \
215 { \
216 build_insn(buf, insn##op, a); \
217 } \
218 UASM_EXPORT_SYMBOL(uasm_i##op);
219
220 #define I_0(op) \
221 Ip_0(op) \
222 { \
223 build_insn(buf, insn##op); \
224 } \
225 UASM_EXPORT_SYMBOL(uasm_i##op);
226
227 I_u2u1s3(_addiu)
228 I_u3u1u2(_addu)
229 I_u2u1u3(_andi)
230 I_u3u1u2(_and)
231 I_u1u2s3(_beq)
232 I_u1u2s3(_beql)
233 I_u1s2(_bgez)
234 I_u1s2(_bgezl)
235 I_u1s2(_bltz)
236 I_u1s2(_bltzl)
237 I_u1u2s3(_bne)
238 I_u2s3u1(_cache)
239 I_u1u2u3(_dmfc0)
240 I_u1u2u3(_dmtc0)
241 I_u2u1s3(_daddiu)
242 I_u3u1u2(_daddu)
243 I_u2u1u3(_dsll)
244 I_u2u1u3(_dsll32)
245 I_u2u1u3(_dsra)
246 I_u2u1u3(_dsrl)
247 I_u2u1u3(_dsrl32)
248 I_u2u1u3(_drotr)
249 I_u2u1u3(_drotr32)
250 I_u3u1u2(_dsubu)
251 I_0(_eret)
252 I_u2u1msbdu3(_ext)
253 I_u2u1msbu3(_ins)
254 I_u1(_j)
255 I_u1(_jal)
256 I_u1(_jr)
257 I_u2s3u1(_ld)
258 I_u2s3u1(_ll)
259 I_u2s3u1(_lld)
260 I_u1s2(_lui)
261 I_u2s3u1(_lw)
262 I_u1u2u3(_mfc0)
263 I_u1u2u3(_mtc0)
264 I_u2u1u3(_ori)
265 I_u3u1u2(_or)
266 I_0(_rfe)
267 I_u2s3u1(_sc)
268 I_u2s3u1(_scd)
269 I_u2s3u1(_sd)
270 I_u2u1u3(_sll)
271 I_u2u1u3(_sra)
272 I_u2u1u3(_srl)
273 I_u2u1u3(_rotr)
274 I_u3u1u2(_subu)
275 I_u2s3u1(_sw)
276 I_0(_tlbp)
277 I_0(_tlbr)
278 I_0(_tlbwi)
279 I_0(_tlbwr)
280 I_u3u1u2(_xor)
281 I_u2u1u3(_xori)
282 I_u2u1msbu3(_dins);
283 I_u2u1msb32u3(_dinsm);
284 I_u1(_syscall);
285 I_u1u2s3(_bbit0);
286 I_u1u2s3(_bbit1);
287 I_u3u1u2(_lwx)
I_u3u1u2(_ldx)288 I_u3u1u2(_ldx)
289
290 #ifdef CONFIG_CPU_CAVIUM_OCTEON
291 #include <asm/octeon/octeon.h>
292 void __uasminit ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
293 unsigned int c)
294 {
295 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
296 /*
297 * As per erratum Core-14449, replace prefetches 0-4,
298 * 6-24 with 'pref 28'.
299 */
300 build_insn(buf, insn_pref, c, 28, b);
301 else
302 build_insn(buf, insn_pref, c, a, b);
303 }
304 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
305 #else
306 I_u2s3u1(_pref)
307 #endif
308
309 /* Handle labels. */
ISAFUNC(uasm_build_label)310 void __uasminit ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid)
311 {
312 (*lab)->addr = addr;
313 (*lab)->lab = lid;
314 (*lab)++;
315 }
316 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));
317
ISAFUNC(uasm_in_compat_space_p)318 int __uasminit ISAFUNC(uasm_in_compat_space_p)(long addr)
319 {
320 /* Is this address in 32bit compat space? */
321 #ifdef CONFIG_64BIT
322 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
323 #else
324 return 1;
325 #endif
326 }
327 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));
328
uasm_rel_highest(long val)329 static int __uasminit uasm_rel_highest(long val)
330 {
331 #ifdef CONFIG_64BIT
332 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
333 #else
334 return 0;
335 #endif
336 }
337
uasm_rel_higher(long val)338 static int __uasminit uasm_rel_higher(long val)
339 {
340 #ifdef CONFIG_64BIT
341 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
342 #else
343 return 0;
344 #endif
345 }
346
ISAFUNC(uasm_rel_hi)347 int __uasminit ISAFUNC(uasm_rel_hi)(long val)
348 {
349 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
350 }
351 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));
352
ISAFUNC(uasm_rel_lo)353 int __uasminit ISAFUNC(uasm_rel_lo)(long val)
354 {
355 return ((val & 0xffff) ^ 0x8000) - 0x8000;
356 }
357 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));
358
ISAFUNC(UASM_i_LA_mostly)359 void __uasminit ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
360 {
361 if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
362 ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
363 if (uasm_rel_higher(addr))
364 ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
365 if (ISAFUNC(uasm_rel_hi(addr))) {
366 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
367 ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
368 ISAFUNC(uasm_rel_hi)(addr));
369 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
370 } else
371 ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
372 } else
373 ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
374 }
375 UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));
376
ISAFUNC(UASM_i_LA)377 void __uasminit ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
378 {
379 ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
380 if (ISAFUNC(uasm_rel_lo(addr))) {
381 if (!ISAFUNC(uasm_in_compat_space_p)(addr))
382 ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
383 ISAFUNC(uasm_rel_lo(addr)));
384 else
385 ISAFUNC(uasm_i_addiu)(buf, rs, rs,
386 ISAFUNC(uasm_rel_lo(addr)));
387 }
388 }
389 UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));
390
391 /* Handle relocations. */
392 void __uasminit
ISAFUNC(uasm_r_mips_pc16)393 ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid)
394 {
395 (*rel)->addr = addr;
396 (*rel)->type = R_MIPS_PC16;
397 (*rel)->lab = lid;
398 (*rel)++;
399 }
400 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));
401
402 static inline void __uasminit
403 __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab);
404
405 void __uasminit
ISAFUNC(uasm_resolve_relocs)406 ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel, struct uasm_label *lab)
407 {
408 struct uasm_label *l;
409
410 for (; rel->lab != UASM_LABEL_INVALID; rel++)
411 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
412 if (rel->lab == l->lab)
413 __resolve_relocs(rel, l);
414 }
415 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));
416
417 void __uasminit
ISAFUNC(uasm_move_relocs)418 ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end, long off)
419 {
420 for (; rel->lab != UASM_LABEL_INVALID; rel++)
421 if (rel->addr >= first && rel->addr < end)
422 rel->addr += off;
423 }
424 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));
425
426 void __uasminit
ISAFUNC(uasm_move_labels)427 ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end, long off)
428 {
429 for (; lab->lab != UASM_LABEL_INVALID; lab++)
430 if (lab->addr >= first && lab->addr < end)
431 lab->addr += off;
432 }
433 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));
434
435 void __uasminit
ISAFUNC(uasm_copy_handler)436 ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab, u32 *first,
437 u32 *end, u32 *target)
438 {
439 long off = (long)(target - first);
440
441 memcpy(target, first, (end - first) * sizeof(u32));
442
443 ISAFUNC(uasm_move_relocs(rel, first, end, off));
444 ISAFUNC(uasm_move_labels(lab, first, end, off));
445 }
446 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));
447
ISAFUNC(uasm_insn_has_bdelay)448 int __uasminit ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr)
449 {
450 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
451 if (rel->addr == addr
452 && (rel->type == R_MIPS_PC16
453 || rel->type == R_MIPS_26))
454 return 1;
455 }
456
457 return 0;
458 }
459 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));
460
461 /* Convenience functions for labeled branches. */
462 void __uasminit
ISAFUNC(uasm_il_bltz)463 ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
464 {
465 uasm_r_mips_pc16(r, *p, lid);
466 ISAFUNC(uasm_i_bltz)(p, reg, 0);
467 }
468 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));
469
470 void __uasminit
ISAFUNC(uasm_il_b)471 ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid)
472 {
473 uasm_r_mips_pc16(r, *p, lid);
474 ISAFUNC(uasm_i_b)(p, 0);
475 }
476 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));
477
478 void __uasminit
ISAFUNC(uasm_il_beqz)479 ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
480 {
481 uasm_r_mips_pc16(r, *p, lid);
482 ISAFUNC(uasm_i_beqz)(p, reg, 0);
483 }
484 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));
485
486 void __uasminit
ISAFUNC(uasm_il_beqzl)487 ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
488 {
489 uasm_r_mips_pc16(r, *p, lid);
490 ISAFUNC(uasm_i_beqzl)(p, reg, 0);
491 }
492 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));
493
494 void __uasminit
ISAFUNC(uasm_il_bne)495 ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1,
496 unsigned int reg2, int lid)
497 {
498 uasm_r_mips_pc16(r, *p, lid);
499 ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
500 }
501 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));
502
503 void __uasminit
ISAFUNC(uasm_il_bnez)504 ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
505 {
506 uasm_r_mips_pc16(r, *p, lid);
507 ISAFUNC(uasm_i_bnez)(p, reg, 0);
508 }
509 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));
510
511 void __uasminit
ISAFUNC(uasm_il_bgezl)512 ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
513 {
514 uasm_r_mips_pc16(r, *p, lid);
515 ISAFUNC(uasm_i_bgezl)(p, reg, 0);
516 }
517 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));
518
519 void __uasminit
ISAFUNC(uasm_il_bgez)520 ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid)
521 {
522 uasm_r_mips_pc16(r, *p, lid);
523 ISAFUNC(uasm_i_bgez)(p, reg, 0);
524 }
525 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));
526
527 void __uasminit
ISAFUNC(uasm_il_bbit0)528 ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg,
529 unsigned int bit, int lid)
530 {
531 uasm_r_mips_pc16(r, *p, lid);
532 ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
533 }
534 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));
535
536 void __uasminit
ISAFUNC(uasm_il_bbit1)537 ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg,
538 unsigned int bit, int lid)
539 {
540 uasm_r_mips_pc16(r, *p, lid);
541 ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
542 }
543 UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));
544