1 /*
2 * Colour AR M64278(VGA) driver for Video4Linux
3 *
4 * Copyright (C) 2003 Takeo Takahashi <takahashi.takeo@renesas.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Some code is taken from AR driver sample program for M3T-M32700UT.
12 *
13 * AR driver sample (M32R SDK):
14 * Copyright (c) 2003 RENESAS TECHNOROGY CORPORATION
15 * AND RENESAS SOLUTIONS CORPORATION
16 * All Rights Reserved.
17 *
18 * 2003-09-01: Support w3cam by Takeo Takahashi
19 */
20
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <linux/fs.h>
26 #include <linux/kernel.h>
27 #include <linux/slab.h>
28 #include <linux/mm.h>
29 #include <linux/sched.h>
30 #include <linux/videodev2.h>
31 #include <media/v4l2-common.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-ioctl.h>
34 #include <media/v4l2-fh.h>
35 #include <linux/mutex.h>
36
37 #include <asm/uaccess.h>
38 #include <asm/m32r.h>
39 #include <asm/io.h>
40 #include <asm/dma.h>
41 #include <asm/byteorder.h>
42
43 #if 0
44 #define DEBUG(n, args...) printk(KERN_INFO args)
45 #define CHECK_LOST 1
46 #else
47 #define DEBUG(n, args...)
48 #define CHECK_LOST 0
49 #endif
50
51 /*
52 * USE_INT is always 0, interrupt mode is not available
53 * on linux due to lack of speed
54 */
55 #define USE_INT 0 /* Don't modify */
56
57 #define VERSION "0.0.5"
58
59 #define ar_inl(addr) inl((unsigned long)(addr))
60 #define ar_outl(val, addr) outl((unsigned long)(val), (unsigned long)(addr))
61
62 extern struct cpuinfo_m32r boot_cpu_data;
63
64 /*
65 * CCD pixel size
66 * Note that M32700UT does not support CIF mode, but QVGA is
67 * supported by M32700UT hardware using VGA mode of AR LSI.
68 *
69 * Supported: VGA (Normal mode, Interlace mode)
70 * QVGA (Always Interlace mode of VGA)
71 *
72 */
73 #define AR_WIDTH_VGA 640
74 #define AR_HEIGHT_VGA 480
75 #define AR_WIDTH_QVGA 320
76 #define AR_HEIGHT_QVGA 240
77 #define MIN_AR_WIDTH AR_WIDTH_QVGA
78 #define MIN_AR_HEIGHT AR_HEIGHT_QVGA
79 #define MAX_AR_WIDTH AR_WIDTH_VGA
80 #define MAX_AR_HEIGHT AR_HEIGHT_VGA
81
82 /* bits & bytes per pixel */
83 #define AR_BITS_PER_PIXEL 16
84 #define AR_BYTES_PER_PIXEL (AR_BITS_PER_PIXEL / 8)
85
86 /* line buffer size */
87 #define AR_LINE_BYTES_VGA (AR_WIDTH_VGA * AR_BYTES_PER_PIXEL)
88 #define AR_LINE_BYTES_QVGA (AR_WIDTH_QVGA * AR_BYTES_PER_PIXEL)
89 #define MAX_AR_LINE_BYTES AR_LINE_BYTES_VGA
90
91 /* frame size & type */
92 #define AR_FRAME_BYTES_VGA \
93 (AR_WIDTH_VGA * AR_HEIGHT_VGA * AR_BYTES_PER_PIXEL)
94 #define AR_FRAME_BYTES_QVGA \
95 (AR_WIDTH_QVGA * AR_HEIGHT_QVGA * AR_BYTES_PER_PIXEL)
96 #define MAX_AR_FRAME_BYTES \
97 (MAX_AR_WIDTH * MAX_AR_HEIGHT * AR_BYTES_PER_PIXEL)
98
99 #define AR_MAX_FRAME 15
100
101 /* capture size */
102 #define AR_SIZE_VGA 0
103 #define AR_SIZE_QVGA 1
104
105 /* capture mode */
106 #define AR_MODE_INTERLACE 0
107 #define AR_MODE_NORMAL 1
108
109 struct ar {
110 struct v4l2_device v4l2_dev;
111 struct video_device vdev;
112 unsigned int start_capture; /* duaring capture in INT. mode. */
113 #if USE_INT
114 unsigned char *line_buff; /* DMA line buffer */
115 #endif
116 unsigned char *frame[MAX_AR_HEIGHT]; /* frame data */
117 short size; /* capture size */
118 short mode; /* capture mode */
119 int width, height;
120 int frame_bytes, line_bytes;
121 wait_queue_head_t wait;
122 struct mutex lock;
123 };
124
125 static struct ar ardev;
126
127 static int video_nr = -1; /* video device number (first free) */
128 static unsigned char yuv[MAX_AR_FRAME_BYTES];
129
130 /* module parameters */
131 /* default frequency */
132 #define DEFAULT_FREQ 50 /* 50 or 75 (MHz) is available as BCLK */
133 static int freq = DEFAULT_FREQ; /* BCLK: available 50 or 70 (MHz) */
134 static int vga; /* default mode(0:QVGA mode, other:VGA mode) */
135 static int vga_interlace; /* 0 is normal mode for, else interlace mode */
136 module_param(freq, int, 0);
137 module_param(vga, int, 0);
138 module_param(vga_interlace, int, 0);
139
wait_for_vsync(void)140 static void wait_for_vsync(void)
141 {
142 while (ar_inl(ARVCR0) & ARVCR0_VDS) /* wait for VSYNC */
143 cpu_relax();
144 while (!(ar_inl(ARVCR0) & ARVCR0_VDS)) /* wait for VSYNC */
145 cpu_relax();
146 }
147
wait_acknowledge(void)148 static void wait_acknowledge(void)
149 {
150 int i;
151
152 for (i = 0; i < 1000; i++)
153 cpu_relax();
154 while (ar_inl(PLDI2CSTS) & PLDI2CSTS_NOACK)
155 cpu_relax();
156 }
157
158 /*******************************************************************
159 * I2C functions
160 *******************************************************************/
iic(int n,unsigned long addr,unsigned long data1,unsigned long data2,unsigned long data3)161 static void iic(int n, unsigned long addr, unsigned long data1, unsigned long data2,
162 unsigned long data3)
163 {
164 int i;
165
166 /* Slave Address */
167 ar_outl(addr, PLDI2CDATA);
168 wait_for_vsync();
169
170 /* Start */
171 ar_outl(1, PLDI2CCND);
172 wait_acknowledge();
173
174 /* Transfer data 1 */
175 ar_outl(data1, PLDI2CDATA);
176 wait_for_vsync();
177 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
178 wait_acknowledge();
179
180 /* Transfer data 2 */
181 ar_outl(data2, PLDI2CDATA);
182 wait_for_vsync();
183 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
184 wait_acknowledge();
185
186 if (n == 3) {
187 /* Transfer data 3 */
188 ar_outl(data3, PLDI2CDATA);
189 wait_for_vsync();
190 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
191 wait_acknowledge();
192 }
193
194 /* Stop */
195 for (i = 0; i < 100; i++)
196 cpu_relax();
197 ar_outl(2, PLDI2CCND);
198 ar_outl(2, PLDI2CCND);
199
200 while (ar_inl(PLDI2CSTS) & PLDI2CSTS_BB)
201 cpu_relax();
202 }
203
204
init_iic(void)205 static void init_iic(void)
206 {
207 DEBUG(1, "init_iic:\n");
208
209 /*
210 * ICU Setting (iic)
211 */
212 /* I2C Setting */
213 ar_outl(0x0, PLDI2CCR); /* I2CCR Disable */
214 ar_outl(0x0300, PLDI2CMOD); /* I2CMOD ACK/8b-data/7b-addr/auto */
215 ar_outl(0x1, PLDI2CACK); /* I2CACK ACK */
216
217 /* I2C CLK */
218 /* 50MH-100k */
219 if (freq == 75)
220 ar_outl(369, PLDI2CFREQ); /* BCLK = 75MHz */
221 else if (freq == 50)
222 ar_outl(244, PLDI2CFREQ); /* BCLK = 50MHz */
223 else
224 ar_outl(244, PLDI2CFREQ); /* default: BCLK = 50MHz */
225 ar_outl(0x1, PLDI2CCR); /* I2CCR Enable */
226 }
227
228 /**************************************************************************
229 *
230 * Video4Linux Interface functions
231 *
232 **************************************************************************/
233
disable_dma(void)234 static inline void disable_dma(void)
235 {
236 ar_outl(0x8000, M32R_DMAEN_PORTL); /* disable DMA0 */
237 }
238
enable_dma(void)239 static inline void enable_dma(void)
240 {
241 ar_outl(0x8080, M32R_DMAEN_PORTL); /* enable DMA0 */
242 }
243
clear_dma_status(void)244 static inline void clear_dma_status(void)
245 {
246 ar_outl(0x8000, M32R_DMAEDET_PORTL); /* clear status */
247 }
248
wait_for_vertical_sync(struct ar * ar,int exp_line)249 static void wait_for_vertical_sync(struct ar *ar, int exp_line)
250 {
251 #if CHECK_LOST
252 int tmout = 10000; /* FIXME */
253 int l;
254
255 /*
256 * check HCOUNT because we cannot check vertical sync.
257 */
258 for (; tmout >= 0; tmout--) {
259 l = ar_inl(ARVHCOUNT);
260 if (l == exp_line)
261 break;
262 }
263 if (tmout < 0)
264 v4l2_err(&ar->v4l2_dev, "lost %d -> %d\n", exp_line, l);
265 #else
266 while (ar_inl(ARVHCOUNT) != exp_line)
267 cpu_relax();
268 #endif
269 }
270
ar_read(struct file * file,char * buf,size_t count,loff_t * ppos)271 static ssize_t ar_read(struct file *file, char *buf, size_t count, loff_t *ppos)
272 {
273 struct ar *ar = video_drvdata(file);
274 long ret = ar->frame_bytes; /* return read bytes */
275 unsigned long arvcr1 = 0;
276 unsigned long flags;
277 unsigned char *p;
278 int h, w;
279 unsigned char *py, *pu, *pv;
280 #if !USE_INT
281 int l;
282 #endif
283
284 DEBUG(1, "ar_read()\n");
285
286 if (ar->size == AR_SIZE_QVGA)
287 arvcr1 |= ARVCR1_QVGA;
288 if (ar->mode == AR_MODE_NORMAL)
289 arvcr1 |= ARVCR1_NORMAL;
290
291 mutex_lock(&ar->lock);
292
293 #if USE_INT
294 local_irq_save(flags);
295 disable_dma();
296 ar_outl(0xa1871300, M32R_DMA0CR0_PORTL);
297 ar_outl(0x01000000, M32R_DMA0CR1_PORTL);
298
299 /* set AR FIFO address as source(BSEL5) */
300 ar_outl(ARDATA32, M32R_DMA0CSA_PORTL);
301 ar_outl(ARDATA32, M32R_DMA0RSA_PORTL);
302 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* destination addr. */
303 ar_outl(ar->line_buff, M32R_DMA0RDA_PORTL); /* reload address */
304 ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL); /* byte count (bytes) */
305 ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL); /* reload count (bytes) */
306
307 /*
308 * Okay, kick AR LSI to invoke an interrupt
309 */
310 ar->start_capture = 0;
311 ar_outl(arvcr1 | ARVCR1_HIEN, ARVCR1);
312 local_irq_restore(flags);
313 /* .... AR interrupts .... */
314 interruptible_sleep_on(&ar->wait);
315 if (signal_pending(current)) {
316 printk(KERN_ERR "arv: interrupted while get frame data.\n");
317 ret = -EINTR;
318 goto out_up;
319 }
320 #else /* ! USE_INT */
321 /* polling */
322 ar_outl(arvcr1, ARVCR1);
323 disable_dma();
324 ar_outl(0x8000, M32R_DMAEDET_PORTL);
325 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
326 ar_outl(0x01000000, M32R_DMA0CR1_PORTL);
327 ar_outl(ARDATA32, M32R_DMA0CSA_PORTL);
328 ar_outl(ARDATA32, M32R_DMA0RSA_PORTL);
329 ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL);
330 ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL);
331
332 local_irq_save(flags);
333 while (ar_inl(ARVHCOUNT) != 0) /* wait for 0 */
334 cpu_relax();
335 if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) {
336 for (h = 0; h < ar->height; h++) {
337 wait_for_vertical_sync(ar, h);
338 if (h < (AR_HEIGHT_VGA/2))
339 l = h << 1;
340 else
341 l = (((h - (AR_HEIGHT_VGA/2)) << 1) + 1);
342 ar_outl(virt_to_phys(ar->frame[l]), M32R_DMA0CDA_PORTL);
343 enable_dma();
344 while (!(ar_inl(M32R_DMAEDET_PORTL) & 0x8000))
345 cpu_relax();
346 disable_dma();
347 clear_dma_status();
348 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
349 }
350 } else {
351 for (h = 0; h < ar->height; h++) {
352 wait_for_vertical_sync(ar, h);
353 ar_outl(virt_to_phys(ar->frame[h]), M32R_DMA0CDA_PORTL);
354 enable_dma();
355 while (!(ar_inl(M32R_DMAEDET_PORTL) & 0x8000))
356 cpu_relax();
357 disable_dma();
358 clear_dma_status();
359 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
360 }
361 }
362 local_irq_restore(flags);
363 #endif /* ! USE_INT */
364
365 /*
366 * convert YUV422 to YUV422P
367 * +--------------------+
368 * | Y0,Y1,... |
369 * | ..............Yn |
370 * +--------------------+
371 * | U0,U1,........Un |
372 * +--------------------+
373 * | V0,V1,........Vn |
374 * +--------------------+
375 */
376 py = yuv;
377 pu = py + (ar->frame_bytes / 2);
378 pv = pu + (ar->frame_bytes / 4);
379 for (h = 0; h < ar->height; h++) {
380 p = ar->frame[h];
381 for (w = 0; w < ar->line_bytes; w += 4) {
382 *py++ = *p++;
383 *pu++ = *p++;
384 *py++ = *p++;
385 *pv++ = *p++;
386 }
387 }
388 if (copy_to_user(buf, yuv, ar->frame_bytes)) {
389 v4l2_err(&ar->v4l2_dev, "failed while copy_to_user yuv.\n");
390 ret = -EFAULT;
391 goto out_up;
392 }
393 DEBUG(1, "ret = %d\n", ret);
394 out_up:
395 mutex_unlock(&ar->lock);
396 return ret;
397 }
398
ar_querycap(struct file * file,void * priv,struct v4l2_capability * vcap)399 static int ar_querycap(struct file *file, void *priv,
400 struct v4l2_capability *vcap)
401 {
402 struct ar *ar = video_drvdata(file);
403
404 strlcpy(vcap->driver, ar->vdev.name, sizeof(vcap->driver));
405 strlcpy(vcap->card, "Colour AR VGA", sizeof(vcap->card));
406 strlcpy(vcap->bus_info, "Platform", sizeof(vcap->bus_info));
407 vcap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE;
408 vcap->capabilities = vcap->device_caps | V4L2_CAP_DEVICE_CAPS;
409 return 0;
410 }
411
ar_enum_input(struct file * file,void * fh,struct v4l2_input * vin)412 static int ar_enum_input(struct file *file, void *fh, struct v4l2_input *vin)
413 {
414 if (vin->index > 0)
415 return -EINVAL;
416 strlcpy(vin->name, "Camera", sizeof(vin->name));
417 vin->type = V4L2_INPUT_TYPE_CAMERA;
418 vin->audioset = 0;
419 vin->tuner = 0;
420 vin->std = V4L2_STD_ALL;
421 vin->status = 0;
422 return 0;
423 }
424
ar_g_input(struct file * file,void * fh,unsigned int * inp)425 static int ar_g_input(struct file *file, void *fh, unsigned int *inp)
426 {
427 *inp = 0;
428 return 0;
429 }
430
ar_s_input(struct file * file,void * fh,unsigned int inp)431 static int ar_s_input(struct file *file, void *fh, unsigned int inp)
432 {
433 return inp ? -EINVAL : 0;
434 }
435
ar_g_fmt_vid_cap(struct file * file,void * fh,struct v4l2_format * fmt)436 static int ar_g_fmt_vid_cap(struct file *file, void *fh, struct v4l2_format *fmt)
437 {
438 struct ar *ar = video_drvdata(file);
439 struct v4l2_pix_format *pix = &fmt->fmt.pix;
440
441 pix->width = ar->width;
442 pix->height = ar->height;
443 pix->pixelformat = V4L2_PIX_FMT_YUV422P;
444 pix->field = (ar->mode == AR_MODE_NORMAL) ? V4L2_FIELD_NONE : V4L2_FIELD_INTERLACED;
445 pix->bytesperline = ar->width;
446 pix->sizeimage = 2 * ar->width * ar->height;
447 /* Just a guess */
448 pix->colorspace = V4L2_COLORSPACE_SMPTE170M;
449 return 0;
450 }
451
ar_try_fmt_vid_cap(struct file * file,void * fh,struct v4l2_format * fmt)452 static int ar_try_fmt_vid_cap(struct file *file, void *fh, struct v4l2_format *fmt)
453 {
454 struct ar *ar = video_drvdata(file);
455 struct v4l2_pix_format *pix = &fmt->fmt.pix;
456
457 if (pix->height <= AR_HEIGHT_QVGA || pix->width <= AR_WIDTH_QVGA) {
458 pix->height = AR_HEIGHT_QVGA;
459 pix->width = AR_WIDTH_QVGA;
460 pix->field = V4L2_FIELD_INTERLACED;
461 } else {
462 pix->height = AR_HEIGHT_VGA;
463 pix->width = AR_WIDTH_VGA;
464 pix->field = vga_interlace ? V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE;
465 }
466 pix->pixelformat = V4L2_PIX_FMT_YUV422P;
467 pix->bytesperline = ar->width;
468 pix->sizeimage = 2 * ar->width * ar->height;
469 /* Just a guess */
470 pix->colorspace = V4L2_COLORSPACE_SMPTE170M;
471 return 0;
472 }
473
ar_s_fmt_vid_cap(struct file * file,void * fh,struct v4l2_format * fmt)474 static int ar_s_fmt_vid_cap(struct file *file, void *fh, struct v4l2_format *fmt)
475 {
476 struct ar *ar = video_drvdata(file);
477 struct v4l2_pix_format *pix = &fmt->fmt.pix;
478 int ret = ar_try_fmt_vid_cap(file, fh, fmt);
479
480 if (ret)
481 return ret;
482 mutex_lock(&ar->lock);
483 ar->width = pix->width;
484 ar->height = pix->height;
485 if (ar->width == AR_WIDTH_VGA) {
486 ar->size = AR_SIZE_VGA;
487 ar->frame_bytes = AR_FRAME_BYTES_VGA;
488 ar->line_bytes = AR_LINE_BYTES_VGA;
489 if (vga_interlace)
490 ar->mode = AR_MODE_INTERLACE;
491 else
492 ar->mode = AR_MODE_NORMAL;
493 } else {
494 ar->size = AR_SIZE_QVGA;
495 ar->frame_bytes = AR_FRAME_BYTES_QVGA;
496 ar->line_bytes = AR_LINE_BYTES_QVGA;
497 ar->mode = AR_MODE_INTERLACE;
498 }
499 /* Ok we figured out what to use from our wide choice */
500 mutex_unlock(&ar->lock);
501 return 0;
502 }
503
ar_enum_fmt_vid_cap(struct file * file,void * fh,struct v4l2_fmtdesc * fmt)504 static int ar_enum_fmt_vid_cap(struct file *file, void *fh, struct v4l2_fmtdesc *fmt)
505 {
506 static struct v4l2_fmtdesc formats[] = {
507 { 0, 0, 0,
508 "YUV 4:2:2 Planar", V4L2_PIX_FMT_YUV422P,
509 { 0, 0, 0, 0 }
510 },
511 };
512 enum v4l2_buf_type type = fmt->type;
513
514 if (fmt->index > 0)
515 return -EINVAL;
516
517 *fmt = formats[fmt->index];
518 fmt->type = type;
519 return 0;
520 }
521
522 #if USE_INT
523 /*
524 * Interrupt handler
525 */
ar_interrupt(int irq,void * dev)526 static void ar_interrupt(int irq, void *dev)
527 {
528 struct ar *ar = dev;
529 unsigned int line_count;
530 unsigned int line_number;
531 unsigned int arvcr1;
532
533 line_count = ar_inl(ARVHCOUNT); /* line number */
534 if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) {
535 /* operations for interlace mode */
536 if (line_count < (AR_HEIGHT_VGA / 2)) /* even line */
537 line_number = (line_count << 1);
538 else /* odd line */
539 line_number =
540 (((line_count - (AR_HEIGHT_VGA / 2)) << 1) + 1);
541 } else {
542 line_number = line_count;
543 }
544
545 if (line_number == 0) {
546 /*
547 * It is an interrupt for line 0.
548 * we have to start capture.
549 */
550 disable_dma();
551 #if 0
552 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* needless? */
553 #endif
554 memcpy(ar->frame[0], ar->line_buff, ar->line_bytes);
555 #if 0
556 ar_outl(0xa1861300, M32R_DMA0CR0_PORTL);
557 #endif
558 enable_dma();
559 ar->start_capture = 1; /* during capture */
560 return;
561 }
562
563 if (ar->start_capture == 1 && line_number <= (ar->height - 1)) {
564 disable_dma();
565 memcpy(ar->frame[line_number], ar->line_buff, ar->line_bytes);
566
567 /*
568 * if captured all line of a frame, disable AR interrupt
569 * and wake a process up.
570 */
571 if (line_number == (ar->height - 1)) { /* end of line */
572
573 ar->start_capture = 0;
574
575 /* disable AR interrupt request */
576 arvcr1 = ar_inl(ARVCR1);
577 arvcr1 &= ~ARVCR1_HIEN; /* clear int. flag */
578 ar_outl(arvcr1, ARVCR1); /* disable */
579 wake_up_interruptible(&ar->wait);
580 } else {
581 #if 0
582 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL);
583 ar_outl(0xa1861300, M32R_DMA0CR0_PORTL);
584 #endif
585 enable_dma();
586 }
587 }
588 }
589 #endif
590
591 /*
592 * ar_initialize()
593 * ar_initialize() is called by video_register_device() and
594 * initializes AR LSI and peripherals.
595 *
596 * -1 is returned in all failures.
597 * 0 is returned in success.
598 *
599 */
ar_initialize(struct ar * ar)600 static int ar_initialize(struct ar *ar)
601 {
602 unsigned long cr = 0;
603 int i, found = 0;
604
605 DEBUG(1, "ar_initialize:\n");
606
607 /*
608 * initialize AR LSI
609 */
610 ar_outl(0, ARVCR0); /* assert reset of AR LSI */
611 for (i = 0; i < 0x18; i++) /* wait for over 10 cycles @ 27MHz */
612 cpu_relax();
613 ar_outl(ARVCR0_RST, ARVCR0); /* negate reset of AR LSI (enable) */
614 for (i = 0; i < 0x40d; i++) /* wait for over 420 cycles @ 27MHz */
615 cpu_relax();
616
617 /* AR uses INT3 of CPU as interrupt pin. */
618 ar_outl(ARINTSEL_INT3, ARINTSEL);
619
620 if (ar->size == AR_SIZE_QVGA)
621 cr |= ARVCR1_QVGA;
622 if (ar->mode == AR_MODE_NORMAL)
623 cr |= ARVCR1_NORMAL;
624 ar_outl(cr, ARVCR1);
625
626 /*
627 * Initialize IIC so that CPU can communicate with AR LSI,
628 * and send boot commands to AR LSI.
629 */
630 init_iic();
631
632 for (i = 0; i < 0x100000; i++) { /* > 0xa1d10, 56ms */
633 if ((ar_inl(ARVCR0) & ARVCR0_VDS)) { /* VSYNC */
634 found = 1;
635 break;
636 }
637 }
638
639 if (found == 0)
640 return -ENODEV;
641
642 v4l2_info(&ar->v4l2_dev, "Initializing ");
643
644 iic(2, 0x78, 0x11, 0x01, 0x00); /* start */
645 iic(3, 0x78, 0x12, 0x00, 0x06);
646 iic(3, 0x78, 0x12, 0x12, 0x30);
647 iic(3, 0x78, 0x12, 0x15, 0x58);
648 iic(3, 0x78, 0x12, 0x17, 0x30);
649 printk(KERN_CONT ".");
650 iic(3, 0x78, 0x12, 0x1a, 0x97);
651 iic(3, 0x78, 0x12, 0x1b, 0xff);
652 iic(3, 0x78, 0x12, 0x1c, 0xff);
653 iic(3, 0x78, 0x12, 0x26, 0x10);
654 iic(3, 0x78, 0x12, 0x27, 0x00);
655 printk(KERN_CONT ".");
656 iic(2, 0x78, 0x34, 0x02, 0x00);
657 iic(2, 0x78, 0x7a, 0x10, 0x00);
658 iic(2, 0x78, 0x80, 0x39, 0x00);
659 iic(2, 0x78, 0x81, 0xe6, 0x00);
660 iic(2, 0x78, 0x8d, 0x00, 0x00);
661 printk(KERN_CONT ".");
662 iic(2, 0x78, 0x8e, 0x0c, 0x00);
663 iic(2, 0x78, 0x8f, 0x00, 0x00);
664 #if 0
665 iic(2, 0x78, 0x90, 0x00, 0x00); /* AWB on=1 off=0 */
666 #endif
667 iic(2, 0x78, 0x93, 0x01, 0x00);
668 iic(2, 0x78, 0x94, 0xcd, 0x00);
669 iic(2, 0x78, 0x95, 0x00, 0x00);
670 printk(KERN_CONT ".");
671 iic(2, 0x78, 0x96, 0xa0, 0x00);
672 iic(2, 0x78, 0x97, 0x00, 0x00);
673 iic(2, 0x78, 0x98, 0x60, 0x00);
674 iic(2, 0x78, 0x99, 0x01, 0x00);
675 iic(2, 0x78, 0x9a, 0x19, 0x00);
676 printk(KERN_CONT ".");
677 iic(2, 0x78, 0x9b, 0x02, 0x00);
678 iic(2, 0x78, 0x9c, 0xe8, 0x00);
679 iic(2, 0x78, 0x9d, 0x02, 0x00);
680 iic(2, 0x78, 0x9e, 0x2e, 0x00);
681 iic(2, 0x78, 0xb8, 0x78, 0x00);
682 iic(2, 0x78, 0xba, 0x05, 0x00);
683 #if 0
684 iic(2, 0x78, 0x83, 0x8c, 0x00); /* brightness */
685 #endif
686 printk(KERN_CONT ".");
687
688 /* color correction */
689 iic(3, 0x78, 0x49, 0x00, 0x95); /* a */
690 iic(3, 0x78, 0x49, 0x01, 0x96); /* b */
691 iic(3, 0x78, 0x49, 0x03, 0x85); /* c */
692 iic(3, 0x78, 0x49, 0x04, 0x97); /* d */
693 iic(3, 0x78, 0x49, 0x02, 0x7e); /* e(Lo) */
694 iic(3, 0x78, 0x49, 0x05, 0xa4); /* f(Lo) */
695 iic(3, 0x78, 0x49, 0x06, 0x04); /* e(Hi) */
696 iic(3, 0x78, 0x49, 0x07, 0x04); /* e(Hi) */
697 iic(2, 0x78, 0x48, 0x01, 0x00); /* on=1 off=0 */
698
699 printk(KERN_CONT ".");
700 iic(2, 0x78, 0x11, 0x00, 0x00); /* end */
701 printk(KERN_CONT " done\n");
702 return 0;
703 }
704
705
706 /****************************************************************************
707 *
708 * Video4Linux Module functions
709 *
710 ****************************************************************************/
711
712 static const struct v4l2_file_operations ar_fops = {
713 .owner = THIS_MODULE,
714 .open = v4l2_fh_open,
715 .release = v4l2_fh_release,
716 .read = ar_read,
717 .unlocked_ioctl = video_ioctl2,
718 };
719
720 static const struct v4l2_ioctl_ops ar_ioctl_ops = {
721 .vidioc_querycap = ar_querycap,
722 .vidioc_g_input = ar_g_input,
723 .vidioc_s_input = ar_s_input,
724 .vidioc_enum_input = ar_enum_input,
725 .vidioc_enum_fmt_vid_cap = ar_enum_fmt_vid_cap,
726 .vidioc_g_fmt_vid_cap = ar_g_fmt_vid_cap,
727 .vidioc_s_fmt_vid_cap = ar_s_fmt_vid_cap,
728 .vidioc_try_fmt_vid_cap = ar_try_fmt_vid_cap,
729 };
730
731 #define ALIGN4(x) ((((int)(x)) & 0x3) == 0)
732
ar_init(void)733 static int __init ar_init(void)
734 {
735 struct ar *ar;
736 struct v4l2_device *v4l2_dev;
737 int ret;
738 int i;
739
740 ar = &ardev;
741 v4l2_dev = &ar->v4l2_dev;
742 strlcpy(v4l2_dev->name, "arv", sizeof(v4l2_dev->name));
743 v4l2_info(v4l2_dev, "Colour AR VGA driver %s\n", VERSION);
744
745 ret = v4l2_device_register(NULL, v4l2_dev);
746 if (ret < 0) {
747 v4l2_err(v4l2_dev, "Could not register v4l2_device\n");
748 return ret;
749 }
750 ret = -EIO;
751
752 #if USE_INT
753 /* allocate a DMA buffer for 1 line. */
754 ar->line_buff = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL | GFP_DMA);
755 if (ar->line_buff == NULL || !ALIGN4(ar->line_buff)) {
756 v4l2_err(v4l2_dev, "buffer allocation failed for DMA.\n");
757 ret = -ENOMEM;
758 goto out_end;
759 }
760 #endif
761 /* allocate buffers for a frame */
762 for (i = 0; i < MAX_AR_HEIGHT; i++) {
763 ar->frame[i] = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL);
764 if (ar->frame[i] == NULL || !ALIGN4(ar->frame[i])) {
765 v4l2_err(v4l2_dev, "buffer allocation failed for frame.\n");
766 ret = -ENOMEM;
767 goto out_line_buff;
768 }
769 }
770
771 strlcpy(ar->vdev.name, "Colour AR VGA", sizeof(ar->vdev.name));
772 ar->vdev.v4l2_dev = v4l2_dev;
773 ar->vdev.fops = &ar_fops;
774 ar->vdev.ioctl_ops = &ar_ioctl_ops;
775 ar->vdev.release = video_device_release_empty;
776 set_bit(V4L2_FL_USE_FH_PRIO, &ar->vdev.flags);
777 video_set_drvdata(&ar->vdev, ar);
778
779 if (vga) {
780 ar->width = AR_WIDTH_VGA;
781 ar->height = AR_HEIGHT_VGA;
782 ar->size = AR_SIZE_VGA;
783 ar->frame_bytes = AR_FRAME_BYTES_VGA;
784 ar->line_bytes = AR_LINE_BYTES_VGA;
785 if (vga_interlace)
786 ar->mode = AR_MODE_INTERLACE;
787 else
788 ar->mode = AR_MODE_NORMAL;
789 } else {
790 ar->width = AR_WIDTH_QVGA;
791 ar->height = AR_HEIGHT_QVGA;
792 ar->size = AR_SIZE_QVGA;
793 ar->frame_bytes = AR_FRAME_BYTES_QVGA;
794 ar->line_bytes = AR_LINE_BYTES_QVGA;
795 ar->mode = AR_MODE_INTERLACE;
796 }
797 mutex_init(&ar->lock);
798 init_waitqueue_head(&ar->wait);
799
800 #if USE_INT
801 if (request_irq(M32R_IRQ_INT3, ar_interrupt, 0, "arv", ar)) {
802 v4l2_err("request_irq(%d) failed.\n", M32R_IRQ_INT3);
803 ret = -EIO;
804 goto out_irq;
805 }
806 #endif
807
808 if (ar_initialize(ar) != 0) {
809 v4l2_err(v4l2_dev, "M64278 not found.\n");
810 ret = -ENODEV;
811 goto out_dev;
812 }
813
814 /*
815 * ok, we can initialize h/w according to parameters,
816 * so register video device as a frame grabber type.
817 * device is named "video[0-64]".
818 * video_register_device() initializes h/w using ar_initialize().
819 */
820 if (video_register_device(&ar->vdev, VFL_TYPE_GRABBER, video_nr) != 0) {
821 /* return -1, -ENFILE(full) or others */
822 v4l2_err(v4l2_dev, "register video (Colour AR) failed.\n");
823 ret = -ENODEV;
824 goto out_dev;
825 }
826
827 v4l2_info(v4l2_dev, "%s: Found M64278 VGA (IRQ %d, Freq %dMHz).\n",
828 video_device_node_name(&ar->vdev), M32R_IRQ_INT3, freq);
829
830 return 0;
831
832 out_dev:
833 #if USE_INT
834 free_irq(M32R_IRQ_INT3, ar);
835
836 out_irq:
837 #endif
838 for (i = 0; i < MAX_AR_HEIGHT; i++)
839 kfree(ar->frame[i]);
840
841 out_line_buff:
842 #if USE_INT
843 kfree(ar->line_buff);
844
845 out_end:
846 #endif
847 v4l2_device_unregister(&ar->v4l2_dev);
848 return ret;
849 }
850
851
ar_init_module(void)852 static int __init ar_init_module(void)
853 {
854 freq = (boot_cpu_data.bus_clock / 1000000);
855 printk(KERN_INFO "arv: Bus clock %d\n", freq);
856 if (freq != 50 && freq != 75)
857 freq = DEFAULT_FREQ;
858 return ar_init();
859 }
860
ar_cleanup_module(void)861 static void __exit ar_cleanup_module(void)
862 {
863 struct ar *ar;
864 int i;
865
866 ar = &ardev;
867 video_unregister_device(&ar->vdev);
868 #if USE_INT
869 free_irq(M32R_IRQ_INT3, ar);
870 #endif
871 for (i = 0; i < MAX_AR_HEIGHT; i++)
872 kfree(ar->frame[i]);
873 #if USE_INT
874 kfree(ar->line_buff);
875 #endif
876 v4l2_device_unregister(&ar->v4l2_dev);
877 }
878
879 module_init(ar_init_module);
880 module_exit(ar_cleanup_module);
881
882 MODULE_AUTHOR("Takeo Takahashi <takahashi.takeo@renesas.com>");
883 MODULE_DESCRIPTION("Colour AR M64278(VGA) for Video4Linux");
884 MODULE_LICENSE("GPL");
885 MODULE_VERSION(VERSION);
886