1 /*
2 * Copyright (c) 2012 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/interrupt.h>
18
19 #include "wil6210.h"
20
21 /**
22 * Theory of operation:
23 *
24 * There is ISR pseudo-cause register,
25 * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
26 * Its bits represents OR'ed bits from 3 real ISR registers:
27 * TX, RX, and MISC.
28 *
29 * Registers may be configured to either "write 1 to clear" or
30 * "clear on read" mode
31 *
32 * When handling interrupt, one have to mask/unmask interrupts for the
33 * real ISR registers, or hardware may malfunction.
34 *
35 */
36
37 #define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL)
38 #define WIL6210_IMC_RX BIT_DMA_EP_RX_ICR_RX_DONE
39 #define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE | \
40 BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
41 #define WIL6210_IMC_MISC (ISR_MISC_FW_READY | \
42 ISR_MISC_MBOX_EVT | \
43 ISR_MISC_FW_ERROR)
44
45 #define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
46 BIT_DMA_PSEUDO_CAUSE_TX | \
47 BIT_DMA_PSEUDO_CAUSE_MISC))
48
49 #if defined(CONFIG_WIL6210_ISR_COR)
50 /* configure to Clear-On-Read mode */
51 #define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL)
52
wil_icr_clear(u32 x,void __iomem * addr)53 static inline void wil_icr_clear(u32 x, void __iomem *addr)
54 {
55 }
56 #else /* defined(CONFIG_WIL6210_ISR_COR) */
57 /* configure to Write-1-to-Clear mode */
58 #define WIL_ICR_ICC_VALUE (0UL)
59
wil_icr_clear(u32 x,void __iomem * addr)60 static inline void wil_icr_clear(u32 x, void __iomem *addr)
61 {
62 iowrite32(x, addr);
63 }
64 #endif /* defined(CONFIG_WIL6210_ISR_COR) */
65
wil_ioread32_and_clear(void __iomem * addr)66 static inline u32 wil_ioread32_and_clear(void __iomem *addr)
67 {
68 u32 x = ioread32(addr);
69
70 wil_icr_clear(x, addr);
71
72 return x;
73 }
74
wil6210_mask_irq_tx(struct wil6210_priv * wil)75 static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
76 {
77 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
78 HOSTADDR(RGF_DMA_EP_TX_ICR) +
79 offsetof(struct RGF_ICR, IMS));
80 }
81
wil6210_mask_irq_rx(struct wil6210_priv * wil)82 static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
83 {
84 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
85 HOSTADDR(RGF_DMA_EP_RX_ICR) +
86 offsetof(struct RGF_ICR, IMS));
87 }
88
wil6210_mask_irq_misc(struct wil6210_priv * wil)89 static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
90 {
91 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
92 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
93 offsetof(struct RGF_ICR, IMS));
94 }
95
wil6210_mask_irq_pseudo(struct wil6210_priv * wil)96 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
97 {
98 wil_dbg_irq(wil, "%s()\n", __func__);
99
100 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
101 HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
102
103 clear_bit(wil_status_irqen, &wil->status);
104 }
105
wil6210_unmask_irq_tx(struct wil6210_priv * wil)106 static void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
107 {
108 iowrite32(WIL6210_IMC_TX, wil->csr +
109 HOSTADDR(RGF_DMA_EP_TX_ICR) +
110 offsetof(struct RGF_ICR, IMC));
111 }
112
wil6210_unmask_irq_rx(struct wil6210_priv * wil)113 static void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
114 {
115 iowrite32(WIL6210_IMC_RX, wil->csr +
116 HOSTADDR(RGF_DMA_EP_RX_ICR) +
117 offsetof(struct RGF_ICR, IMC));
118 }
119
wil6210_unmask_irq_misc(struct wil6210_priv * wil)120 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
121 {
122 iowrite32(WIL6210_IMC_MISC, wil->csr +
123 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
124 offsetof(struct RGF_ICR, IMC));
125 }
126
wil6210_unmask_irq_pseudo(struct wil6210_priv * wil)127 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
128 {
129 wil_dbg_irq(wil, "%s()\n", __func__);
130
131 set_bit(wil_status_irqen, &wil->status);
132
133 iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr +
134 HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
135 }
136
wil6210_disable_irq(struct wil6210_priv * wil)137 void wil6210_disable_irq(struct wil6210_priv *wil)
138 {
139 wil_dbg_irq(wil, "%s()\n", __func__);
140
141 wil6210_mask_irq_tx(wil);
142 wil6210_mask_irq_rx(wil);
143 wil6210_mask_irq_misc(wil);
144 wil6210_mask_irq_pseudo(wil);
145 }
146
wil6210_enable_irq(struct wil6210_priv * wil)147 void wil6210_enable_irq(struct wil6210_priv *wil)
148 {
149 wil_dbg_irq(wil, "%s()\n", __func__);
150
151 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
152 offsetof(struct RGF_ICR, ICC));
153 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
154 offsetof(struct RGF_ICR, ICC));
155 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
156 offsetof(struct RGF_ICR, ICC));
157
158 wil6210_unmask_irq_pseudo(wil);
159 wil6210_unmask_irq_tx(wil);
160 wil6210_unmask_irq_rx(wil);
161 wil6210_unmask_irq_misc(wil);
162 }
163
wil6210_irq_rx(int irq,void * cookie)164 static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
165 {
166 struct wil6210_priv *wil = cookie;
167 u32 isr = wil_ioread32_and_clear(wil->csr +
168 HOSTADDR(RGF_DMA_EP_RX_ICR) +
169 offsetof(struct RGF_ICR, ICR));
170
171 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
172
173 if (!isr) {
174 wil_err(wil, "spurious IRQ: RX\n");
175 return IRQ_NONE;
176 }
177
178 wil6210_mask_irq_rx(wil);
179
180 if (isr & BIT_DMA_EP_RX_ICR_RX_DONE) {
181 wil_dbg_irq(wil, "RX done\n");
182 isr &= ~BIT_DMA_EP_RX_ICR_RX_DONE;
183 wil_rx_handle(wil);
184 }
185
186 if (isr)
187 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
188
189 wil6210_unmask_irq_rx(wil);
190
191 return IRQ_HANDLED;
192 }
193
wil6210_irq_tx(int irq,void * cookie)194 static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
195 {
196 struct wil6210_priv *wil = cookie;
197 u32 isr = wil_ioread32_and_clear(wil->csr +
198 HOSTADDR(RGF_DMA_EP_TX_ICR) +
199 offsetof(struct RGF_ICR, ICR));
200
201 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
202
203 if (!isr) {
204 wil_err(wil, "spurious IRQ: TX\n");
205 return IRQ_NONE;
206 }
207
208 wil6210_mask_irq_tx(wil);
209
210 if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) {
211 uint i;
212 wil_dbg_irq(wil, "TX done\n");
213 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
214 for (i = 0; i < 24; i++) {
215 u32 mask = BIT_DMA_EP_TX_ICR_TX_DONE_N(i);
216 if (isr & mask) {
217 isr &= ~mask;
218 wil_dbg_irq(wil, "TX done(%i)\n", i);
219 wil_tx_complete(wil, i);
220 }
221 }
222 }
223
224 if (isr)
225 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
226
227 wil6210_unmask_irq_tx(wil);
228
229 return IRQ_HANDLED;
230 }
231
wil_notify_fw_error(struct wil6210_priv * wil)232 static void wil_notify_fw_error(struct wil6210_priv *wil)
233 {
234 struct device *dev = &wil_to_ndev(wil)->dev;
235 char *envp[3] = {
236 [0] = "SOURCE=wil6210",
237 [1] = "EVENT=FW_ERROR",
238 [2] = NULL,
239 };
240 kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
241 }
242
wil_cache_mbox_regs(struct wil6210_priv * wil)243 static void wil_cache_mbox_regs(struct wil6210_priv *wil)
244 {
245 /* make shadow copy of registers that should not change on run time */
246 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
247 sizeof(struct wil6210_mbox_ctl));
248 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
249 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
250 }
251
wil6210_irq_misc(int irq,void * cookie)252 static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
253 {
254 struct wil6210_priv *wil = cookie;
255 u32 isr = wil_ioread32_and_clear(wil->csr +
256 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
257 offsetof(struct RGF_ICR, ICR));
258
259 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
260
261 if (!isr) {
262 wil_err(wil, "spurious IRQ: MISC\n");
263 return IRQ_NONE;
264 }
265
266 wil6210_mask_irq_misc(wil);
267
268 if (isr & ISR_MISC_FW_ERROR) {
269 wil_err(wil, "Firmware error detected\n");
270 clear_bit(wil_status_fwready, &wil->status);
271 /*
272 * do not clear @isr here - we do 2-nd part in thread
273 * there, user space get notified, and it should be done
274 * in non-atomic context
275 */
276 }
277
278 if (isr & ISR_MISC_FW_READY) {
279 wil_dbg_irq(wil, "IRQ: FW ready\n");
280 wil_cache_mbox_regs(wil);
281 set_bit(wil_status_reset_done, &wil->status);
282 /**
283 * Actual FW ready indicated by the
284 * WMI_FW_READY_EVENTID
285 */
286 isr &= ~ISR_MISC_FW_READY;
287 }
288
289 wil->isr_misc = isr;
290
291 if (isr) {
292 return IRQ_WAKE_THREAD;
293 } else {
294 wil6210_unmask_irq_misc(wil);
295 return IRQ_HANDLED;
296 }
297 }
298
wil6210_irq_misc_thread(int irq,void * cookie)299 static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
300 {
301 struct wil6210_priv *wil = cookie;
302 u32 isr = wil->isr_misc;
303
304 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
305
306 if (isr & ISR_MISC_FW_ERROR) {
307 wil_notify_fw_error(wil);
308 isr &= ~ISR_MISC_FW_ERROR;
309 }
310
311 if (isr & ISR_MISC_MBOX_EVT) {
312 wil_dbg_irq(wil, "MBOX event\n");
313 wmi_recv_cmd(wil);
314 isr &= ~ISR_MISC_MBOX_EVT;
315 }
316
317 if (isr)
318 wil_err(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
319
320 wil->isr_misc = 0;
321
322 wil6210_unmask_irq_misc(wil);
323
324 return IRQ_HANDLED;
325 }
326
327 /**
328 * thread IRQ handler
329 */
wil6210_thread_irq(int irq,void * cookie)330 static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
331 {
332 struct wil6210_priv *wil = cookie;
333
334 wil_dbg_irq(wil, "Thread IRQ\n");
335 /* Discover real IRQ cause */
336 if (wil->isr_misc)
337 wil6210_irq_misc_thread(irq, cookie);
338
339 wil6210_unmask_irq_pseudo(wil);
340
341 return IRQ_HANDLED;
342 }
343
344 /* DEBUG
345 * There is subtle bug in hardware that causes IRQ to raise when it should be
346 * masked. It is quite rare and hard to debug.
347 *
348 * Catch irq issue if it happens and print all I can.
349 */
wil6210_debug_irq_mask(struct wil6210_priv * wil,u32 pseudo_cause)350 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
351 {
352 if (!test_bit(wil_status_irqen, &wil->status)) {
353 u32 icm_rx = wil_ioread32_and_clear(wil->csr +
354 HOSTADDR(RGF_DMA_EP_RX_ICR) +
355 offsetof(struct RGF_ICR, ICM));
356 u32 icr_rx = wil_ioread32_and_clear(wil->csr +
357 HOSTADDR(RGF_DMA_EP_RX_ICR) +
358 offsetof(struct RGF_ICR, ICR));
359 u32 imv_rx = ioread32(wil->csr +
360 HOSTADDR(RGF_DMA_EP_RX_ICR) +
361 offsetof(struct RGF_ICR, IMV));
362 u32 icm_tx = wil_ioread32_and_clear(wil->csr +
363 HOSTADDR(RGF_DMA_EP_TX_ICR) +
364 offsetof(struct RGF_ICR, ICM));
365 u32 icr_tx = wil_ioread32_and_clear(wil->csr +
366 HOSTADDR(RGF_DMA_EP_TX_ICR) +
367 offsetof(struct RGF_ICR, ICR));
368 u32 imv_tx = ioread32(wil->csr +
369 HOSTADDR(RGF_DMA_EP_TX_ICR) +
370 offsetof(struct RGF_ICR, IMV));
371 u32 icm_misc = wil_ioread32_and_clear(wil->csr +
372 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
373 offsetof(struct RGF_ICR, ICM));
374 u32 icr_misc = wil_ioread32_and_clear(wil->csr +
375 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
376 offsetof(struct RGF_ICR, ICR));
377 u32 imv_misc = ioread32(wil->csr +
378 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
379 offsetof(struct RGF_ICR, IMV));
380 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
381 "Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
382 "Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
383 "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
384 pseudo_cause,
385 icm_rx, icr_rx, imv_rx,
386 icm_tx, icr_tx, imv_tx,
387 icm_misc, icr_misc, imv_misc);
388
389 return -EINVAL;
390 }
391
392 return 0;
393 }
394
wil6210_hardirq(int irq,void * cookie)395 static irqreturn_t wil6210_hardirq(int irq, void *cookie)
396 {
397 irqreturn_t rc = IRQ_HANDLED;
398 struct wil6210_priv *wil = cookie;
399 u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE));
400
401 /**
402 * pseudo_cause is Clear-On-Read, no need to ACK
403 */
404 if ((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff))
405 return IRQ_NONE;
406
407 /* FIXME: IRQ mask debug */
408 if (wil6210_debug_irq_mask(wil, pseudo_cause))
409 return IRQ_NONE;
410
411 wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
412
413 wil6210_mask_irq_pseudo(wil);
414
415 /* Discover real IRQ cause
416 * There are 2 possible phases for every IRQ:
417 * - hard IRQ handler called right here
418 * - threaded handler called later
419 *
420 * Hard IRQ handler reads and clears ISR.
421 *
422 * If threaded handler requested, hard IRQ handler
423 * returns IRQ_WAKE_THREAD and saves ISR register value
424 * for the threaded handler use.
425 *
426 * voting for wake thread - need at least 1 vote
427 */
428 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
429 (wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
430 rc = IRQ_WAKE_THREAD;
431
432 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
433 (wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
434 rc = IRQ_WAKE_THREAD;
435
436 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
437 (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
438 rc = IRQ_WAKE_THREAD;
439
440 /* if thread is requested, it will unmask IRQ */
441 if (rc != IRQ_WAKE_THREAD)
442 wil6210_unmask_irq_pseudo(wil);
443
444 return rc;
445 }
446
wil6210_request_3msi(struct wil6210_priv * wil,int irq)447 static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
448 {
449 int rc;
450 /*
451 * IRQ's are in the following order:
452 * - Tx
453 * - Rx
454 * - Misc
455 */
456
457 rc = request_irq(irq, wil6210_irq_tx, IRQF_SHARED,
458 WIL_NAME"_tx", wil);
459 if (rc)
460 return rc;
461
462 rc = request_irq(irq + 1, wil6210_irq_rx, IRQF_SHARED,
463 WIL_NAME"_rx", wil);
464 if (rc)
465 goto free0;
466
467 rc = request_threaded_irq(irq + 2, wil6210_irq_misc,
468 wil6210_irq_misc_thread,
469 IRQF_SHARED, WIL_NAME"_misc", wil);
470 if (rc)
471 goto free1;
472
473 return 0;
474 /* error branch */
475 free1:
476 free_irq(irq + 1, wil);
477 free0:
478 free_irq(irq, wil);
479
480 return rc;
481 }
482
wil6210_init_irq(struct wil6210_priv * wil,int irq)483 int wil6210_init_irq(struct wil6210_priv *wil, int irq)
484 {
485 int rc;
486 if (wil->n_msi == 3)
487 rc = wil6210_request_3msi(wil, irq);
488 else
489 rc = request_threaded_irq(irq, wil6210_hardirq,
490 wil6210_thread_irq,
491 wil->n_msi ? 0 : IRQF_SHARED,
492 WIL_NAME, wil);
493 if (rc)
494 return rc;
495
496 wil6210_enable_irq(wil);
497
498 return 0;
499 }
500
wil6210_fini_irq(struct wil6210_priv * wil,int irq)501 void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
502 {
503 wil6210_disable_irq(wil);
504 free_irq(irq, wil);
505 if (wil->n_msi == 3) {
506 free_irq(irq + 1, wil);
507 free_irq(irq + 2, wil);
508 }
509 }
510