1 /*
2 * Interrupt handling for IPR-based IRQ.
3 *
4 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
5 * Copyright (C) 2000 Kazumoto Kojima
6 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
7 * Copyright (C) 2006 Paul Mundt
8 *
9 * Supported system:
10 * On-chip supporting modules (TMU, RTC, etc.).
11 * On-chip supporting modules for SH7709/SH7709A/SH7729.
12 * Hitachi SolutionEngine external I/O:
13 * MS7709SE01, MS7709ASE01, and MS7750SE01
14 *
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
17 * for more details.
18 */
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/irq.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/topology.h>
26
get_ipr_desc(struct irq_data * data)27 static inline struct ipr_desc *get_ipr_desc(struct irq_data *data)
28 {
29 struct irq_chip *chip = irq_data_get_irq_chip(data);
30 return container_of(chip, struct ipr_desc, chip);
31 }
32
disable_ipr_irq(struct irq_data * data)33 static void disable_ipr_irq(struct irq_data *data)
34 {
35 struct ipr_data *p = irq_data_get_irq_chip_data(data);
36 unsigned long addr = get_ipr_desc(data)->ipr_offsets[p->ipr_idx];
37 /* Set the priority in IPR to 0 */
38 __raw_writew(__raw_readw(addr) & (0xffff ^ (0xf << p->shift)), addr);
39 (void)__raw_readw(addr); /* Read back to flush write posting */
40 }
41
enable_ipr_irq(struct irq_data * data)42 static void enable_ipr_irq(struct irq_data *data)
43 {
44 struct ipr_data *p = irq_data_get_irq_chip_data(data);
45 unsigned long addr = get_ipr_desc(data)->ipr_offsets[p->ipr_idx];
46 /* Set priority in IPR back to original value */
47 __raw_writew(__raw_readw(addr) | (p->priority << p->shift), addr);
48 }
49
50 /*
51 * The shift value is now the number of bits to shift, not the number of
52 * bits/4. This is to make it easier to read the value directly from the
53 * datasheets. The IPR address is calculated using the ipr_offset table.
54 */
register_ipr_controller(struct ipr_desc * desc)55 void register_ipr_controller(struct ipr_desc *desc)
56 {
57 int i;
58
59 desc->chip.irq_mask = disable_ipr_irq;
60 desc->chip.irq_unmask = enable_ipr_irq;
61
62 for (i = 0; i < desc->nr_irqs; i++) {
63 struct ipr_data *p = desc->ipr_data + i;
64 int res;
65
66 BUG_ON(p->ipr_idx >= desc->nr_offsets);
67 BUG_ON(!desc->ipr_offsets[p->ipr_idx]);
68
69 res = irq_alloc_desc_at(p->irq, numa_node_id());
70 if (unlikely(res != p->irq && res != -EEXIST)) {
71 printk(KERN_INFO "can not get irq_desc for %d\n",
72 p->irq);
73 continue;
74 }
75
76 disable_irq_nosync(p->irq);
77 irq_set_chip_and_handler_name(p->irq, &desc->chip,
78 handle_level_irq, "level");
79 irq_set_chip_data(p->irq, p);
80 disable_ipr_irq(irq_get_irq_data(p->irq));
81 }
82 }
83 EXPORT_SYMBOL(register_ipr_controller);
84