1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 7 * 8 * Multiprocessor Subsystem Register Definitions 9 * 10 */ 11 #ifndef _ASM_GCMPREGS_H 12 #define _ASM_GCMPREGS_H 13 14 15 /* Offsets to major blocks within GCMP from GCMP base */ 16 #define GCMP_GCB_OFS 0x0000 /* Global Control Block */ 17 #define GCMP_CLCB_OFS 0x2000 /* Core Local Control Block */ 18 #define GCMP_COCB_OFS 0x4000 /* Core Other Control Block */ 19 #define GCMP_GDB_OFS 0x8000 /* Global Debug Block */ 20 21 /* Offsets to individual GCMP registers from GCMP base */ 22 #define GCMPOFS(block, tag, reg) \ 23 (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) 24 #define GCMPOFSn(block, tag, reg, n) \ 25 (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n)) 26 27 #define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg) 28 #define GCMPGCBOFSn(reg, n) GCMPOFSn(GCB, GCB, reg, n) 29 #define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg) 30 #define GCMPCLCBOFSn(reg, n) GCMPOFSn(CLCB, CCB, reg, n) 31 #define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg) 32 #define GCMPCOCBOFSn(reg, n) GCMPOFSn(COCB, CCB, reg, n) 33 #define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg) 34 35 /* GCMP register access */ 36 #define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg)) 37 #define GCMPGCBhi(reg) REGP(_gcmp_base, (GCMPGCBOFS(reg) + 4)) 38 #define GCMPGCBlo(reg) GCMPGCB(reg) 39 //#define GCMPGCBaddr(reg) REGA(_gcmp_base, GCMPGCBOFS(reg)) 40 #if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR) 41 #define GCMPGCBaddr(reg) ((((phys_addr_t)(GCMPGCBhi(reg))) << 32) | \ 42 GCMPGCBlo(reg)) 43 #define GCMPGCBaddrWrite(reg,val) (GCMPGCBhi(reg) = (u32)((phys_addr_t)(val) >> 32), \ 44 GCMPGCBlo(reg) = (u32)(val)) 45 #else 46 #define GCMPGCBaddr(reg) GCMPGCB(reg) 47 #define GCMPGCBaddrWrite(reg,val) (GCMPGCB(reg) = (u32)(val)) 48 #endif 49 #define GCMPGCBn(reg, n) REGP(_gcmp_base, GCMPGCBOFSn(reg, n)) 50 #define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg)) 51 #define GCMPCLCBn(reg, n) REGP(_gcmp_base, GCMPCLCBOFSn(reg, n)) 52 #define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg)) 53 #define GCMPCOCBhi(reg) REGP(_gcmp_base, (GCMPCOCBOFS(reg) + 4)) 54 #define GCMPCOCBlo(reg) GCMPCOCB(reg) 55 #define GCMPCOCBn(reg, n) REGP(_gcmp_base, GCMPCOCBOFSn(reg, n)) 56 #define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg)) 57 58 /* Mask generation */ 59 #define GCMPMSK(block, reg, bits) (MSK(bits)<<GCMP_##block##_##reg##_SHF) 60 #define GCMPGCBMSK(reg, bits) GCMPMSK(GCB, reg, bits) 61 #define GCMPCCBMSK(reg, bits) GCMPMSK(CCB, reg, bits) 62 #define GCMPGDBMSK(reg, bits) GCMPMSK(GDB, reg, bits) 63 64 /* GCB registers */ 65 #define GCMP_GCB_GC_OFS 0x0000 /* Global Config Register */ 66 #define GCMP_GCB_GC_NUMIOCU_SHF 8 67 #define GCMP_GCB_GC_NUMIOCU_MSK GCMPGCBMSK(GC_NUMIOCU, 4) 68 #define GCMP_GCB_GC_NUMCORES_SHF 0 69 #define GCMP_GCB_GC_NUMCORES_MSK GCMPGCBMSK(GC_NUMCORES, 8) 70 #define GCMP_GCB_GCMPB_OFS 0x0008 /* Global GCMP Base */ 71 #define GCMP_GCB_GCMPB_GCMPBASE_SHF 15 72 #ifndef CONFIG_64BIT 73 #define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17) 74 #else 75 #define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 32) 76 #endif 77 #define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0 78 #define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2) 79 #define GCMP_GCB_GCMPB_CMDEFTGT_DISABLED 0 80 #define GCMP_GCB_GCMPB_CMDEFTGT_MEM 1 81 #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 82 #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 83 #define GCMP_GCB_GCMC_OFS 0x0010 /* Global CM Control */ 84 #define GCMP_GCB_GCMC2_OFS 0x0018 /* Global CM Control2/CM3 Alt Control */ 85 #define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */ 86 #define GCMP_GCB_GCSRAP_CMACCESS_SHF 0 87 #define GCMP_GCB_GCSRAP_CMACCESS_MSK GCMPGCBMSK(GCSRAP_CMACCESS, 8) 88 #define GCMP_GCB_GCMPREV_OFS 0x0030 /* GCMP Revision Register */ 89 #define GCMP_GCB_GCMPREV_MAJOR_SHF 8 90 #define GCMP_GCB_GCMPREV_MAJOR_MSK GCMPGCBMSK(GCMPREV_MAJOR, 8) 91 #define GCMP_GCB_GCMPREV_MINOR_SHF 0 92 #define GCMP_GCB_GCMPREV_MINOR_MSK GCMPGCBMSK(GCMPREV_MINOR, 8) 93 #define GCMP_GCB_GCMECTL_OFS 0x0038 /* Global CM3 Error Control */ 94 #define GCMP_GCB_GCMEM_OFS 0x0040 /* Global CM Error Mask */ 95 #define GCMP_GCB_GCMEC_OFS 0x0048 /* Global CM Error Cause */ 96 #define GCMP_GCB_GMEC_ERROR_TYPE_SHF 27 97 #define GCMP_GCB_GMEC_ERROR_TYPE_MSK GCMPGCBMSK(GMEC_ERROR_TYPE, 5) 98 #define GCMP_GCB_GMEC_ERROR_INFO_SHF 0 99 #define GCMP_GCB_GMEC_ERROR_INFO_MSK GCMPGCBMSK(GMEC_ERROR_INFO, 27) 100 #define GCMP_GCB_GCMEA_OFS 0x0050 /* Global CM Error Address */ 101 #define GCMP_GCB_GCMEO_OFS 0x0058 /* Global CM Error Multiple */ 102 #define GCMP_GCB_GMEO_ERROR_2ND_SHF 0 103 #define GCMP_GCB_GMEO_ERROR_2ND_MSK GCMPGCBMSK(GMEO_ERROR_2ND, 5) 104 #define GCMP_GCB_GCMCUS_OFS 0x0060 /* GCR Custom Base */ 105 #define GCMP_GCB_GCMCST_OFS 0x0068 /* GCR Custom Status */ 106 #define GCMP_GCB_GCML2S_OFS 0x0070 /* Global L2 only Sync Register */ 107 #define GCMP_GCB_GCML2S_EN_SHF 0 108 #define GCMP_GCB_GCML2S_EN_MSK GCMPGCBMSK(GCML2S_EN, 1) 109 #define GCMP_GCB_GICBA_OFS 0x0080 /* Global Interrupt Controller Base Address */ 110 #define GCMP_GCB_GICBA_BASE_SHF 17 111 #define GCMP_GCB_GICBA_BASE_MSK GCMPGCBMSK(GICBA_BASE, 15) 112 #define GCMP_GCB_GICBA_EN_SHF 0 113 #define GCMP_GCB_GICBA_EN_MSK GCMPGCBMSK(GICBA_EN, 1) 114 #define GCMP_GCB_CPCBA_OFS 0x0088 /* CPC Base Address */ 115 #define GCMP_GCB_CPCBA_SHF 15 116 #define GCMP_GCB_CPCBA_MSK GCMPGCBMSK(CPCBA, 17) 117 #define GCMP_GCB_CPCBA_EN_SHF 0 118 #define GCMP_GCB_CPCBA_EN_MSK GCMPGCBMSK(CPCBA_EN, 1) 119 120 #define GCMP_GCB_GICST_OFS 0x00D0 /* Global Interrupt Controller Status */ 121 #define GCMP_GCB_GICST_EN_SHF 0 122 #define GCMP_GCB_GICST_EN_MSK GCMPGCBMSK(GICST_EN, 1) 123 #define GCMP_GCB_GCSHREV_OFS 0x00E0 /* Cache Revision */ 124 #define GCMP_GCB_CPCST_OFS 0x00F0 /* CPC Status */ 125 #define GCMP_GCB_CPCST_EN_SHF 0 126 #define GCMP_GCB_CPCST_EN_MSK GCMPGCBMSK(CPCST_EN, 1) 127 128 #define GCMP_GCB_IOCBASE_OFS 0x0100 /* IOCU Base Address */ 129 #define GCMP_GCB_IOST_OFS 0x0108 /* IOMMU Status */ 130 #define GCMP_GCB_G3CSRAP_OFS 0x0120 /* CM3 CSR Access Privilege Register */ 131 #define GCMP_GCB_L2CONFIG_OFS 0x0130 /* CM3 L3 Config */ 132 #define GCMP_GCB_L2CONFIG_ASSOC_SHF 0 133 #define GCMP_GCB_L2CONFIG_ASSOC_MASK GCMPGCBMSK(L2CONFIG_ASSOC, 8) 134 #define GCMP_GCB_L2CONFIG_LSIZE_SHF 8 135 #define GCMP_GCB_L2CONFIG_LSIZE_MASK GCMPGCBMSK(L2CONFIG_LSIZE, 4) 136 #define GCMP_GCB_L2CONFIG_SSIZE_SHF 12 137 #define GCMP_GCB_L2CONFIG_SSIZE_MASK GCMPGCBMSK(L2CONFIG_SSIZE, 4) 138 #define GCMP_GCB_L2CONFIG_BYPASS_SHF 20 139 #define GCMP_GCB_L2CONFIG_BYPASS_MASK GCMPGCBMSK(L2CONFIG_BYPASS, 1) 140 141 #define GCMP_GCB_SYSCONF_OFS 0x0140 /* CM3 SYS Config */ 142 #define GCMP_GCB_SYSCONF2_OFS 0x0150 /* CM3 SYS Config2 */ 143 #define GCMP_GCB_SYSCONF2_VPWIDTH_SHF 0 144 #define GCMP_GCB_SYSCONF2_VPWIDTH_MASK GCMPGCBMSK(SYSCONF2_VPWIDTH, 4) 145 146 /* GCB Regions */ 147 #define GCMP_GCB_CMxBASE_OFS(n) (0x0090+16*(n)) /* Global Region[0-3] Base Address */ 148 #define GCMP_GCB_CMxBASE_BASE_SHF 16 149 #define GCMP_GCB_CMxBASE_BASE_MSK GCMPGCBMSK(CMxBASE_BASE, 16) 150 #define GCMP_GCB_CMxMASK_OFS(n) (0x0098+16*(n)) /* Global Region[0-3] Address Mask */ 151 #define GCMP_GCB_CMxMASK_MASK_SHF 16 152 #define GCMP_GCB_CMxMASK_MASK_MSK GCMPGCBMSK(CMxMASK_MASK, 16) 153 #define GCMP_GCB_CMxMASK_CMREGTGT_SHF 0 154 #define GCMP_GCB_CMxMASK_CMREGTGT_MSK GCMPGCBMSK(CMxMASK_CMREGTGT, 2) 155 #define GCMP_GCB_CMxMASK_CMREGTGT_MEM 0 156 #define GCMP_GCB_CMxMASK_CMREGTGT_MEM1 1 157 #define GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2 158 #define GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3 159 160 #define GCMP_GCB_GAOR0BA_OFS 0x0190 /* Attribute-Only Region0 Base Address */ 161 #define GCMP_GCB_GAOR0MASK_OFS 0x0198 /* Attribute-Only Region0 Mask */ 162 #define GCMP_GCB_GAOR1BA_OFS 0x01A0 /* Attribute-Only Region1 Base Address */ 163 #define GCMP_GCB_GAOR1MASK_OFS 0x01A8 /* Attribute-Only Region1 Mask */ 164 165 #define GCMP_GCB_IOCUREV_OFS 0x0200 /* IOCU Revision */ 166 167 #define GCMP_GCB_GAOR2BA_OFS 0x0210 /* Attribute-Only Region2 Base Address */ 168 #define GCMP_GCB_GAOR2MASK_OFS 0x0218 /* Attribute-Only Region2 Mask */ 169 #define GCMP_GCB_GAOR3BA_OFS 0x0220 /* Attribute-Only Region3 Base Address */ 170 #define GCMP_GCB_GAOR3MASK_OFS 0x0228 /* Attribute-Only Region3 Mask */ 171 #define GCMP_GCB_L2RAMCONF_OFS 0x0240 /* CM3 L2 RAM Configuration */ 172 #define GCMP_GCB_SCRATCH0_OFS 0x0280 /* CM3 Scratch 0 */ 173 #define GCMP_GCB_SCRATCH1_OFS 0x0288 /* CM3 Scratch 1 */ 174 #define GCMP_GCB_GCML2P_OFS 0x0300 /* L2 Prefetch Control */ 175 #define GCMP_GCB_GCML2P_PAGE_MASK 0xfffff000 /* ... page mask */ 176 #define GCMP_GCB_GCML2P_PFTEN 0x00000100 /* L2 Prefetch Enable */ 177 #define GCMP_GCB_GCML2P_NPFT 0x000000ff /* N.of L2 Prefetch */ 178 #define GCMP_GCB_GCML2PB_OFS 0x0308 /* L2 Prefetch Control B */ 179 #define GCMP_GCB_GCML2PB_CODE_PFTEN 0x00000100 /* L2 Code Prefetch Enable */ 180 #define GCMP_GCB_L2PREF_OFS 0x0320 /* CM3 L2 Prefetch Tuning */ 181 #define GCMP_GCB_L2PREFAT0_OFS 0x0340 /* CM3 L2 Prefetch Tuning A Tier 0 */ 182 #define GCMP_GCB_L2PREFBT0_OFS 0x0348 /* CM3 L2 Prefetch Tuning B Tier 0 */ 183 #define GCMP_GCB_L2PREFAT1_OFS 0x0360 /* CM3 L2 Prefetch Tuning A Tier 1 */ 184 #define GCMP_GCB_L2PREFBT1_OFS 0x0368 /* CM3 L2 Prefetch Tuning B Tier 1 */ 185 #define GCMP_GCB_L2PREFAT2_OFS 0x0380 /* CM3 L2 Prefetch Tuning A Tier 2 */ 186 #define GCMP_GCB_L2PREFBT2_OFS 0x0388 /* CM3 L2 Prefetch Tuning B Tier 2 */ 187 #define GCMP_GCB_L2PREFAT3_OFS 0x03A0 /* CM3 L2 Prefetch Tuning A Tier 3 */ 188 #define GCMP_GCB_L2PREFBT3_OFS 0x03A8 /* CM3 L2 Prefetch Tuning B Tier 3 */ 189 #define GCMP_GCB_L2PREFAT4_OFS 0x03C0 /* CM3 L2 Prefetch Tuning A Tier 4 */ 190 #define GCMP_GCB_L2PREFBT4_OFS 0x03C8 /* CM3 L2 Prefetch Tuning B Tier 4 */ 191 #define GCMP_GCB_L2TRCADDR_OFS 0x0600 /* CM3 L2 Tag RAM Cache OP Addr */ 192 #define GCMP_GCB_L2TRCST_OFS 0x0608 /* CM3 L2 Tag RAM Cache OP State */ 193 #define GCMP_GCB_L2DRCOP_OFS 0x0610 /* CM3 L2 DATA RAM Cache OP */ 194 #define GCMP_GCB_L2TDECCOP_OFS 0x0618 /* CM3 L2 Tag and DATA ECC Cache OP */ 195 #define GCMP_GCB_BEVBASE_OFS 0x0680 /* CM3 BEV Base */ 196 197 /* Core local/Core other control block registers */ 198 #define GCMP_CCB_RESETR_OFS 0x0000 /* Reset Release */ 199 #define GCMP_CCB_RESETR_INRESET_SHF 0 200 #define GCMP_CCB_RESETR_INRESET_MSK GCMPCCBMSK(RESETR_INRESET, 16) 201 #define GCMP_CCB_COHENB_OFS 0x0008 /* CM3 Coherence Enable */ 202 #define GCMP_CCB_COHCTL_OFS 0x0008 /* Coherence Control */ 203 #define GCMP_CCB_COHCTL_DOMAIN_SHF 0 204 #define GCMP_CCB_COHCTL_DOMAIN_MSK GCMPCCBMSK(COHCTL_DOMAIN, 8) 205 #define GCMP_CCB_COHCTL_DOMAIN_ENABLE (GCMP_CCB_COHCTL_DOMAIN_MSK) 206 #define GCMP_CCB_CFG_OFS 0x0010 /* Config */ 207 #define GCMP_CCB_CFG_IOCUTYPE_SHF 10 208 #define GCMP_CCB_CFG_IOCUTYPE_MSK GCMPCCBMSK(CFG_IOCUTYPE, 2) 209 #define GCMP_CCB_CFG_IOCUTYPE_CPU 0 210 #define GCMP_CCB_CFG_IOCUTYPE_NCIOCU 1 211 #define GCMP_CCB_CFG_IOCUTYPE_CIOCU 2 212 #define GCMP_CCB_CFG_NUMVPE_SHF 0 213 #define GCMP_CCB_CFG_NUMVPE_MSK GCMPCCBMSK(CFG_NUMVPE, 10) 214 #define GCMP_CCB_OTHER_OFS 0x0018 /* Other Address */ 215 #define GCMP_CCB_OTHER_CORENUM_SHF 16 216 #define GCMP_CCB_OTHER_CORENUM_MSK GCMPCCBMSK(OTHER_CORENUM, 16) 217 #define GCMP_CCB_RESETBASE_OFS 0x0020 /* Reset Exception Base */ 218 #define GCMP_CCB_RESETBASE_BEV_SHF 12 219 #define GCMP_CCB_RESETBASE_BEV_MSK GCMPCCBMSK(RESETBASE_BEV, 20) 220 #define GCMP_CCB_RESETBASEEXT_OFS 0x0030 /* Reset Exception Base Extention */ 221 #define GCMP_CCB_RESETEXTBASE_BEV_SHF 20 222 #define GCMP_CCB_RESETEXTBASE_BEV_MASK_MSK GCMPCCBMSK(RESETEXTBASE_BEV, 8) 223 #define GCMP_CCB_RESETEXTBASE_LOWBITS_SHF 0 224 #define GCMP_CCB_RESETEXTBASE_BEV_MASK_LOWBITS GCMPCCBMSK(RESETEXTBASE_LOWBITS, 20) 225 #define GCMP_CCB_ID_OFS 0x0028 /* Identification */ 226 #define GCMP_CCB_DINTGROUP_OFS 0x0030 /* DINT Group Participate */ 227 #define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */ 228 229 #define GCMP_CCB_TCIDxPRI_OFS(n) (0x0040+8*(n)) /* TCID x PRIORITY */ 230 231 extern int __init gcmp_probe(unsigned long, unsigned long); 232 extern void __init gcmp_setregion(int, unsigned long, unsigned long, int); 233 #ifdef CONFIG_MIPS_CMP 234 extern int __init gcmp_niocu(void); 235 extern int gcmp_present; 236 extern int gcmp3_present; 237 #define GCR3_OTHER(core,vpe) ((core << 8) | vpe) 238 #define GCR3_OTHER_CPU_DATA(cpu) ((cpu_data[cpu].core << 8) | cpu_data[cpu].vpe_id) 239 #else 240 #define gcmp_niocu(x) (0) 241 #define gcmp_present (0) 242 #define gcmp3_present (0) 243 #endif 244 extern unsigned long _gcmp_base; 245 #define GCMP_L2SYNC_OFFSET 0x8100 246 247 #endif /* _ASM_GCMPREGS_H */ 248