1 /*
2 * SH7785 Setup
3 *
4 * Copyright (C) 2007 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
14 #include <linux/io.h>
15 #include <linux/mm.h>
16 #include <linux/sh_dma.h>
17 #include <linux/sh_timer.h>
18 #include <linux/sh_intc.h>
19 #include <asm/mmzone.h>
20 #include <cpu/dma-register.h>
21
22 static struct plat_sci_port scif0_platform_data = {
23 .mapbase = 0xffea0000,
24 .flags = UPF_BOOT_AUTOCONF,
25 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
26 .scbrr_algo_id = SCBRR_ALGO_1,
27 .type = PORT_SCIF,
28 .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)),
29 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
30 };
31
32 static struct platform_device scif0_device = {
33 .name = "sh-sci",
34 .id = 0,
35 .dev = {
36 .platform_data = &scif0_platform_data,
37 },
38 };
39
40 static struct plat_sci_port scif1_platform_data = {
41 .mapbase = 0xffeb0000,
42 .flags = UPF_BOOT_AUTOCONF,
43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
44 .scbrr_algo_id = SCBRR_ALGO_1,
45 .type = PORT_SCIF,
46 .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)),
47 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
48 };
49
50 static struct platform_device scif1_device = {
51 .name = "sh-sci",
52 .id = 1,
53 .dev = {
54 .platform_data = &scif1_platform_data,
55 },
56 };
57
58 static struct plat_sci_port scif2_platform_data = {
59 .mapbase = 0xffec0000,
60 .flags = UPF_BOOT_AUTOCONF,
61 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
62 .scbrr_algo_id = SCBRR_ALGO_1,
63 .type = PORT_SCIF,
64 .irqs = SCIx_IRQ_MUXED(evt2irq(0x980)),
65 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
66 };
67
68 static struct platform_device scif2_device = {
69 .name = "sh-sci",
70 .id = 2,
71 .dev = {
72 .platform_data = &scif2_platform_data,
73 },
74 };
75
76 static struct plat_sci_port scif3_platform_data = {
77 .mapbase = 0xffed0000,
78 .flags = UPF_BOOT_AUTOCONF,
79 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
80 .scbrr_algo_id = SCBRR_ALGO_1,
81 .type = PORT_SCIF,
82 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)),
83 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
84 };
85
86 static struct platform_device scif3_device = {
87 .name = "sh-sci",
88 .id = 3,
89 .dev = {
90 .platform_data = &scif3_platform_data,
91 },
92 };
93
94 static struct plat_sci_port scif4_platform_data = {
95 .mapbase = 0xffee0000,
96 .flags = UPF_BOOT_AUTOCONF,
97 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
98 .scbrr_algo_id = SCBRR_ALGO_1,
99 .type = PORT_SCIF,
100 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)),
101 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
102 };
103
104 static struct platform_device scif4_device = {
105 .name = "sh-sci",
106 .id = 4,
107 .dev = {
108 .platform_data = &scif4_platform_data,
109 },
110 };
111
112 static struct plat_sci_port scif5_platform_data = {
113 .mapbase = 0xffef0000,
114 .flags = UPF_BOOT_AUTOCONF,
115 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1,
116 .scbrr_algo_id = SCBRR_ALGO_1,
117 .type = PORT_SCIF,
118 .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)),
119 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
120 };
121
122 static struct platform_device scif5_device = {
123 .name = "sh-sci",
124 .id = 5,
125 .dev = {
126 .platform_data = &scif5_platform_data,
127 },
128 };
129
130 static struct sh_timer_config tmu0_platform_data = {
131 .channel_offset = 0x04,
132 .timer_bit = 0,
133 .clockevent_rating = 200,
134 };
135
136 static struct resource tmu0_resources[] = {
137 [0] = {
138 .start = 0xffd80008,
139 .end = 0xffd80013,
140 .flags = IORESOURCE_MEM,
141 },
142 [1] = {
143 .start = evt2irq(0x580),
144 .flags = IORESOURCE_IRQ,
145 },
146 };
147
148 static struct platform_device tmu0_device = {
149 .name = "sh_tmu",
150 .id = 0,
151 .dev = {
152 .platform_data = &tmu0_platform_data,
153 },
154 .resource = tmu0_resources,
155 .num_resources = ARRAY_SIZE(tmu0_resources),
156 };
157
158 static struct sh_timer_config tmu1_platform_data = {
159 .channel_offset = 0x10,
160 .timer_bit = 1,
161 .clocksource_rating = 200,
162 };
163
164 static struct resource tmu1_resources[] = {
165 [0] = {
166 .start = 0xffd80014,
167 .end = 0xffd8001f,
168 .flags = IORESOURCE_MEM,
169 },
170 [1] = {
171 .start = evt2irq(0x5a0),
172 .flags = IORESOURCE_IRQ,
173 },
174 };
175
176 static struct platform_device tmu1_device = {
177 .name = "sh_tmu",
178 .id = 1,
179 .dev = {
180 .platform_data = &tmu1_platform_data,
181 },
182 .resource = tmu1_resources,
183 .num_resources = ARRAY_SIZE(tmu1_resources),
184 };
185
186 static struct sh_timer_config tmu2_platform_data = {
187 .channel_offset = 0x1c,
188 .timer_bit = 2,
189 };
190
191 static struct resource tmu2_resources[] = {
192 [0] = {
193 .start = 0xffd80020,
194 .end = 0xffd8002f,
195 .flags = IORESOURCE_MEM,
196 },
197 [1] = {
198 .start = evt2irq(0x5c0),
199 .flags = IORESOURCE_IRQ,
200 },
201 };
202
203 static struct platform_device tmu2_device = {
204 .name = "sh_tmu",
205 .id = 2,
206 .dev = {
207 .platform_data = &tmu2_platform_data,
208 },
209 .resource = tmu2_resources,
210 .num_resources = ARRAY_SIZE(tmu2_resources),
211 };
212
213 static struct sh_timer_config tmu3_platform_data = {
214 .channel_offset = 0x04,
215 .timer_bit = 0,
216 };
217
218 static struct resource tmu3_resources[] = {
219 [0] = {
220 .start = 0xffdc0008,
221 .end = 0xffdc0013,
222 .flags = IORESOURCE_MEM,
223 },
224 [1] = {
225 .start = evt2irq(0xe00),
226 .flags = IORESOURCE_IRQ,
227 },
228 };
229
230 static struct platform_device tmu3_device = {
231 .name = "sh_tmu",
232 .id = 3,
233 .dev = {
234 .platform_data = &tmu3_platform_data,
235 },
236 .resource = tmu3_resources,
237 .num_resources = ARRAY_SIZE(tmu3_resources),
238 };
239
240 static struct sh_timer_config tmu4_platform_data = {
241 .channel_offset = 0x10,
242 .timer_bit = 1,
243 };
244
245 static struct resource tmu4_resources[] = {
246 [0] = {
247 .start = 0xffdc0014,
248 .end = 0xffdc001f,
249 .flags = IORESOURCE_MEM,
250 },
251 [1] = {
252 .start = evt2irq(0xe20),
253 .flags = IORESOURCE_IRQ,
254 },
255 };
256
257 static struct platform_device tmu4_device = {
258 .name = "sh_tmu",
259 .id = 4,
260 .dev = {
261 .platform_data = &tmu4_platform_data,
262 },
263 .resource = tmu4_resources,
264 .num_resources = ARRAY_SIZE(tmu4_resources),
265 };
266
267 static struct sh_timer_config tmu5_platform_data = {
268 .channel_offset = 0x1c,
269 .timer_bit = 2,
270 };
271
272 static struct resource tmu5_resources[] = {
273 [0] = {
274 .start = 0xffdc0020,
275 .end = 0xffdc002b,
276 .flags = IORESOURCE_MEM,
277 },
278 [1] = {
279 .start = evt2irq(0xe40),
280 .flags = IORESOURCE_IRQ,
281 },
282 };
283
284 static struct platform_device tmu5_device = {
285 .name = "sh_tmu",
286 .id = 5,
287 .dev = {
288 .platform_data = &tmu5_platform_data,
289 },
290 .resource = tmu5_resources,
291 .num_resources = ARRAY_SIZE(tmu5_resources),
292 };
293
294 /* DMA */
295 static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
296 {
297 .offset = 0,
298 .dmars = 0,
299 .dmars_bit = 0,
300 }, {
301 .offset = 0x10,
302 .dmars = 0,
303 .dmars_bit = 8,
304 }, {
305 .offset = 0x20,
306 .dmars = 4,
307 .dmars_bit = 0,
308 }, {
309 .offset = 0x30,
310 .dmars = 4,
311 .dmars_bit = 8,
312 }, {
313 .offset = 0x50,
314 .dmars = 8,
315 .dmars_bit = 0,
316 }, {
317 .offset = 0x60,
318 .dmars = 8,
319 .dmars_bit = 8,
320 }
321 };
322
323 static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
324 {
325 .offset = 0,
326 }, {
327 .offset = 0x10,
328 }, {
329 .offset = 0x20,
330 }, {
331 .offset = 0x30,
332 }, {
333 .offset = 0x50,
334 }, {
335 .offset = 0x60,
336 }
337 };
338
339 static const unsigned int ts_shift[] = TS_SHIFT;
340
341 static struct sh_dmae_pdata dma0_platform_data = {
342 .channel = sh7785_dmae0_channels,
343 .channel_num = ARRAY_SIZE(sh7785_dmae0_channels),
344 .ts_low_shift = CHCR_TS_LOW_SHIFT,
345 .ts_low_mask = CHCR_TS_LOW_MASK,
346 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
347 .ts_high_mask = CHCR_TS_HIGH_MASK,
348 .ts_shift = ts_shift,
349 .ts_shift_num = ARRAY_SIZE(ts_shift),
350 .dmaor_init = DMAOR_INIT,
351 };
352
353 static struct sh_dmae_pdata dma1_platform_data = {
354 .channel = sh7785_dmae1_channels,
355 .channel_num = ARRAY_SIZE(sh7785_dmae1_channels),
356 .ts_low_shift = CHCR_TS_LOW_SHIFT,
357 .ts_low_mask = CHCR_TS_LOW_MASK,
358 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
359 .ts_high_mask = CHCR_TS_HIGH_MASK,
360 .ts_shift = ts_shift,
361 .ts_shift_num = ARRAY_SIZE(ts_shift),
362 .dmaor_init = DMAOR_INIT,
363 };
364
365 static struct resource sh7785_dmae0_resources[] = {
366 [0] = {
367 /* Channel registers and DMAOR */
368 .start = 0xfc808020,
369 .end = 0xfc80808f,
370 .flags = IORESOURCE_MEM,
371 },
372 [1] = {
373 /* DMARSx */
374 .start = 0xfc809000,
375 .end = 0xfc80900b,
376 .flags = IORESOURCE_MEM,
377 },
378 {
379 /*
380 * Real DMA error vector is 0x6e0, and channel
381 * vectors are 0x620-0x6c0
382 */
383 .name = "error_irq",
384 .start = evt2irq(0x620),
385 .end = evt2irq(0x620),
386 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
387 },
388 };
389
390 static struct resource sh7785_dmae1_resources[] = {
391 [0] = {
392 /* Channel registers and DMAOR */
393 .start = 0xfcc08020,
394 .end = 0xfcc0808f,
395 .flags = IORESOURCE_MEM,
396 },
397 /* DMAC1 has no DMARS */
398 {
399 /*
400 * Real DMA error vector is 0x940, and channel
401 * vectors are 0x880-0x920
402 */
403 .name = "error_irq",
404 .start = evt2irq(0x880),
405 .end = evt2irq(0x880),
406 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
407 },
408 };
409
410 static struct platform_device dma0_device = {
411 .name = "sh-dma-engine",
412 .id = 0,
413 .resource = sh7785_dmae0_resources,
414 .num_resources = ARRAY_SIZE(sh7785_dmae0_resources),
415 .dev = {
416 .platform_data = &dma0_platform_data,
417 },
418 };
419
420 static struct platform_device dma1_device = {
421 .name = "sh-dma-engine",
422 .id = 1,
423 .resource = sh7785_dmae1_resources,
424 .num_resources = ARRAY_SIZE(sh7785_dmae1_resources),
425 .dev = {
426 .platform_data = &dma1_platform_data,
427 },
428 };
429
430 static struct platform_device *sh7785_devices[] __initdata = {
431 &scif0_device,
432 &scif1_device,
433 &scif2_device,
434 &scif3_device,
435 &scif4_device,
436 &scif5_device,
437 &tmu0_device,
438 &tmu1_device,
439 &tmu2_device,
440 &tmu3_device,
441 &tmu4_device,
442 &tmu5_device,
443 &dma0_device,
444 &dma1_device,
445 };
446
sh7785_devices_setup(void)447 static int __init sh7785_devices_setup(void)
448 {
449 return platform_add_devices(sh7785_devices,
450 ARRAY_SIZE(sh7785_devices));
451 }
452 arch_initcall(sh7785_devices_setup);
453
454 static struct platform_device *sh7785_early_devices[] __initdata = {
455 &scif0_device,
456 &scif1_device,
457 &scif2_device,
458 &scif3_device,
459 &scif4_device,
460 &scif5_device,
461 &tmu0_device,
462 &tmu1_device,
463 &tmu2_device,
464 &tmu3_device,
465 &tmu4_device,
466 &tmu5_device,
467 };
468
plat_early_device_setup(void)469 void __init plat_early_device_setup(void)
470 {
471 early_platform_add_devices(sh7785_early_devices,
472 ARRAY_SIZE(sh7785_early_devices));
473 }
474
475 enum {
476 UNUSED = 0,
477
478 /* interrupt sources */
479
480 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
481 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
482 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
483 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
484
485 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
486 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
487 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
488 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
489
490 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
491 WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
492 HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
493 SCIF2, SCIF3, SCIF4, SCIF5,
494 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
495 SIOF, MMCIF, DU, GDTA,
496 TMU3, TMU4, TMU5,
497 SSI0, SSI1,
498 HAC0, HAC1,
499 FLCTL, GPIO,
500
501 /* interrupt groups */
502
503 TMU012, TMU345
504 };
505
506 static struct intc_vect vectors[] __initdata = {
507 INTC_VECT(WDT, 0x560),
508 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
509 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
510 INTC_VECT(HUDI, 0x600),
511 INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
512 INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
513 INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
514 INTC_VECT(DMAC0, 0x6e0),
515 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
516 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
517 INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
518 INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
519 INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
520 INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
521 INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
522 INTC_VECT(DMAC1, 0x940),
523 INTC_VECT(HSPI, 0x960),
524 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
525 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
526 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
527 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
528 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
529 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
530 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
531 INTC_VECT(SIOF, 0xc00),
532 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
533 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
534 INTC_VECT(DU, 0xd80),
535 INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
536 INTC_VECT(GDTA, 0xde0),
537 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
538 INTC_VECT(TMU5, 0xe40),
539 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
540 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
541 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
542 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
543 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
544 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
545 };
546
547 static struct intc_group groups[] __initdata = {
548 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
549 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
550 };
551
552 static struct intc_mask_reg mask_registers[] __initdata = {
553 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
554 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
555
556 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
557 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
558 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
559 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
560 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
561 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
562 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
563 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
564 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
565
566 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
567 { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
568 FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
569 PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
570 SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
571 };
572
573 static struct intc_prio_reg prio_registers[] __initdata = {
574 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
575 IRQ4, IRQ5, IRQ6, IRQ7 } },
576 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
577 TMU2, TMU2_TICPI } },
578 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
579 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
580 SCIF2, SCIF3 } },
581 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
582 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
583 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
584 PCISERR, PCIINTA } },
585 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
586 PCIINTD, PCIC5 } },
587 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
588 { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
589 { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
590 };
591
592 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
593 mask_registers, prio_registers, NULL);
594
595 /* Support for external interrupt pins in IRQ mode */
596
597 static struct intc_vect vectors_irq0123[] __initdata = {
598 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
599 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
600 };
601
602 static struct intc_vect vectors_irq4567[] __initdata = {
603 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
604 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
605 };
606
607 static struct intc_sense_reg sense_registers[] __initdata = {
608 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
609 IRQ4, IRQ5, IRQ6, IRQ7 } },
610 };
611
612 static struct intc_mask_reg ack_registers[] __initdata = {
613 { 0xffd00024, 0, 32, /* INTREQ */
614 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
615 };
616
617 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
618 vectors_irq0123, NULL, mask_registers,
619 prio_registers, sense_registers, ack_registers);
620
621 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
622 vectors_irq4567, NULL, mask_registers,
623 prio_registers, sense_registers, ack_registers);
624
625 /* External interrupt pins in IRL mode */
626
627 static struct intc_vect vectors_irl0123[] __initdata = {
628 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
629 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
630 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
631 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
632 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
633 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
634 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
635 INTC_VECT(IRL0_HHHL, 0x3c0),
636 };
637
638 static struct intc_vect vectors_irl4567[] __initdata = {
639 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
640 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
641 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
642 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
643 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
644 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
645 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
646 INTC_VECT(IRL4_HHHL, 0xcc0),
647 };
648
649 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
650 NULL, mask_registers, NULL, NULL);
651
652 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
653 NULL, mask_registers, NULL, NULL);
654
655 #define INTC_ICR0 0xffd00000
656 #define INTC_INTMSK0 0xffd00044
657 #define INTC_INTMSK1 0xffd00048
658 #define INTC_INTMSK2 0xffd40080
659 #define INTC_INTMSKCLR1 0xffd00068
660 #define INTC_INTMSKCLR2 0xffd40084
661
plat_irq_setup(void)662 void __init plat_irq_setup(void)
663 {
664 /* disable IRQ3-0 + IRQ7-4 */
665 __raw_writel(0xff000000, INTC_INTMSK0);
666
667 /* disable IRL3-0 + IRL7-4 */
668 __raw_writel(0xc0000000, INTC_INTMSK1);
669 __raw_writel(0xfffefffe, INTC_INTMSK2);
670
671 /* select IRL mode for IRL3-0 + IRL7-4 */
672 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
673
674 /* disable holding function, ie enable "SH-4 Mode" */
675 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
676
677 register_intc_controller(&intc_desc);
678 }
679
plat_irq_setup_pins(int mode)680 void __init plat_irq_setup_pins(int mode)
681 {
682 switch (mode) {
683 case IRQ_MODE_IRQ7654:
684 /* select IRQ mode for IRL7-4 */
685 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
686 register_intc_controller(&intc_desc_irq4567);
687 break;
688 case IRQ_MODE_IRQ3210:
689 /* select IRQ mode for IRL3-0 */
690 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
691 register_intc_controller(&intc_desc_irq0123);
692 break;
693 case IRQ_MODE_IRL7654:
694 /* enable IRL7-4 but don't provide any masking */
695 __raw_writel(0x40000000, INTC_INTMSKCLR1);
696 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
697 break;
698 case IRQ_MODE_IRL3210:
699 /* enable IRL0-3 but don't provide any masking */
700 __raw_writel(0x80000000, INTC_INTMSKCLR1);
701 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
702 break;
703 case IRQ_MODE_IRL7654_MASK:
704 /* enable IRL7-4 and mask using cpu intc controller */
705 __raw_writel(0x40000000, INTC_INTMSKCLR1);
706 register_intc_controller(&intc_desc_irl4567);
707 break;
708 case IRQ_MODE_IRL3210_MASK:
709 /* enable IRL0-3 and mask using cpu intc controller */
710 __raw_writel(0x80000000, INTC_INTMSKCLR1);
711 register_intc_controller(&intc_desc_irl0123);
712 break;
713 default:
714 BUG();
715 }
716 }
717
plat_mem_setup(void)718 void __init plat_mem_setup(void)
719 {
720 /* Register the URAM space as Node 1 */
721 setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
722 }
723