1/* 2 * DTS file for all SPEAr13xx SoCs 3 * 4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com> 5 * 6 * The code contained herein is licensed under the GNU General Public 7 * License. You may obtain a copy of the GNU General Public License 8 * Version 2 or later at the following locations: 9 * 10 * http://www.opensource.org/licenses/gpl-license.html 11 * http://www.gnu.org/copyleft/gpl.html 12 */ 13 14/include/ "skeleton.dtsi" 15 16/ { 17 interrupt-parent = <&gic>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu@0 { 24 compatible = "arm,cortex-a9"; 25 reg = <0>; 26 next-level-cache = <&L2>; 27 }; 28 29 cpu@1 { 30 compatible = "arm,cortex-a9"; 31 reg = <1>; 32 next-level-cache = <&L2>; 33 }; 34 }; 35 36 gic: interrupt-controller@ec801000 { 37 compatible = "arm,cortex-a9-gic"; 38 interrupt-controller; 39 #interrupt-cells = <3>; 40 reg = < 0xec801000 0x1000 >, 41 < 0xec800100 0x0100 >; 42 }; 43 44 pmu { 45 compatible = "arm,cortex-a9-pmu"; 46 interrupts = <0 6 0x04 47 0 7 0x04>; 48 }; 49 50 L2: l2-cache { 51 compatible = "arm,pl310-cache"; 52 reg = <0xed000000 0x1000>; 53 cache-unified; 54 cache-level = <2>; 55 }; 56 57 memory { 58 name = "memory"; 59 device_type = "memory"; 60 reg = <0 0x40000000>; 61 }; 62 63 chosen { 64 bootargs = "console=ttyAMA0,115200"; 65 }; 66 67 cpufreq { 68 compatible = "st,cpufreq-spear"; 69 cpufreq_tbl = < 166000 70 200000 71 250000 72 300000 73 400000 74 500000 75 600000 >; 76 status = "disabled"; 77 }; 78 79 ahb { 80 #address-cells = <1>; 81 #size-cells = <1>; 82 compatible = "simple-bus"; 83 ranges = <0x50000000 0x50000000 0x10000000 84 0xb0000000 0xb0000000 0x10000000 85 0xd0000000 0xd0000000 0x02000000 86 0xd8000000 0xd8000000 0x01000000 87 0xe0000000 0xe0000000 0x10000000>; 88 89 sdhci@b3000000 { 90 compatible = "st,sdhci-spear"; 91 reg = <0xb3000000 0x100>; 92 interrupts = <0 28 0x4>; 93 status = "disabled"; 94 }; 95 96 cf@b2800000 { 97 compatible = "arasan,cf-spear1340"; 98 reg = <0xb2800000 0x1000>; 99 interrupts = <0 29 0x4>; 100 status = "disabled"; 101 dmas = <&dwdma0 0 0 0 0>; 102 dma-names = "data"; 103 }; 104 105 dwdma0: dma@ea800000 { 106 compatible = "snps,dma-spear1340"; 107 reg = <0xea800000 0x1000>; 108 interrupts = <0 19 0x4>; 109 status = "disabled"; 110 111 dma-channels = <8>; 112 #dma-cells = <3>; 113 dma-requests = <32>; 114 chan_allocation_order = <1>; 115 chan_priority = <1>; 116 block_size = <0xfff>; 117 dma-masters = <2>; 118 data_width = <3 3 0 0>; 119 }; 120 121 dma@eb000000 { 122 compatible = "snps,dma-spear1340"; 123 reg = <0xeb000000 0x1000>; 124 interrupts = <0 59 0x4>; 125 status = "disabled"; 126 127 dma-requests = <32>; 128 dma-channels = <8>; 129 dma-masters = <2>; 130 #dma-cells = <3>; 131 chan_allocation_order = <1>; 132 chan_priority = <1>; 133 block_size = <0xfff>; 134 data_width = <3 3 0 0>; 135 }; 136 137 fsmc: flash@b0000000 { 138 compatible = "st,spear600-fsmc-nand"; 139 #address-cells = <1>; 140 #size-cells = <1>; 141 reg = <0xb0000000 0x1000 /* FSMC Register*/ 142 0xb0800000 0x0010 /* NAND Base DATA */ 143 0xb0820000 0x0010 /* NAND Base ADDR */ 144 0xb0810000 0x0010>; /* NAND Base CMD */ 145 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; 146 interrupts = <0 20 0x4 147 0 21 0x4 148 0 22 0x4 149 0 23 0x4>; 150 st,mode = <2>; 151 status = "disabled"; 152 }; 153 154 gmac0: eth@e2000000 { 155 compatible = "st,spear600-gmac"; 156 reg = <0xe2000000 0x8000>; 157 interrupts = <0 33 0x4 158 0 34 0x4>; 159 interrupt-names = "macirq", "eth_wake_irq"; 160 status = "disabled"; 161 }; 162 163 pcm { 164 compatible = "st,pcm-audio"; 165 #address-cells = <0>; 166 #size-cells = <0>; 167 status = "disabled"; 168 }; 169 170 smi: flash@ea000000 { 171 compatible = "st,spear600-smi"; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 reg = <0xea000000 0x1000>; 175 interrupts = <0 30 0x4>; 176 status = "disabled"; 177 }; 178 179 ehci@e4800000 { 180 compatible = "st,spear600-ehci", "usb-ehci"; 181 reg = <0xe4800000 0x1000>; 182 interrupts = <0 64 0x4>; 183 usbh0_id = <0>; 184 status = "disabled"; 185 }; 186 187 ehci@e5800000 { 188 compatible = "st,spear600-ehci", "usb-ehci"; 189 reg = <0xe5800000 0x1000>; 190 interrupts = <0 66 0x4>; 191 usbh1_id = <1>; 192 status = "disabled"; 193 }; 194 195 ohci@e4000000 { 196 compatible = "st,spear600-ohci", "usb-ohci"; 197 reg = <0xe4000000 0x1000>; 198 interrupts = <0 65 0x4>; 199 usbh0_id = <0>; 200 status = "disabled"; 201 }; 202 203 ohci@e5000000 { 204 compatible = "st,spear600-ohci", "usb-ohci"; 205 reg = <0xe5000000 0x1000>; 206 interrupts = <0 67 0x4>; 207 usbh1_id = <1>; 208 status = "disabled"; 209 }; 210 211 apb { 212 #address-cells = <1>; 213 #size-cells = <1>; 214 compatible = "simple-bus"; 215 ranges = <0x50000000 0x50000000 0x10000000 216 0xb0000000 0xb0000000 0x10000000 217 0xd0000000 0xd0000000 0x02000000 218 0xd8000000 0xd8000000 0x01000000 219 0xe0000000 0xe0000000 0x10000000>; 220 221 gpio0: gpio@e0600000 { 222 compatible = "arm,pl061", "arm,primecell"; 223 reg = <0xe0600000 0x1000>; 224 interrupts = <0 24 0x4>; 225 gpio-controller; 226 #gpio-cells = <2>; 227 interrupt-controller; 228 #interrupt-cells = <2>; 229 status = "disabled"; 230 }; 231 232 gpio1: gpio@e0680000 { 233 compatible = "arm,pl061", "arm,primecell"; 234 reg = <0xe0680000 0x1000>; 235 interrupts = <0 25 0x4>; 236 gpio-controller; 237 #gpio-cells = <2>; 238 interrupt-controller; 239 #interrupt-cells = <2>; 240 status = "disabled"; 241 }; 242 243 kbd@e0300000 { 244 compatible = "st,spear300-kbd"; 245 reg = <0xe0300000 0x1000>; 246 interrupts = <0 52 0x4>; 247 status = "disabled"; 248 }; 249 250 i2c0: i2c@e0280000 { 251 #address-cells = <1>; 252 #size-cells = <0>; 253 compatible = "snps,designware-i2c"; 254 reg = <0xe0280000 0x1000>; 255 interrupts = <0 41 0x4>; 256 status = "disabled"; 257 }; 258 259 i2s@e0180000 { 260 compatible = "st,designware-i2s"; 261 reg = <0xe0180000 0x1000>; 262 interrupt-names = "play_irq", "record_irq"; 263 interrupts = <0 10 0x4 264 0 11 0x4 >; 265 status = "disabled"; 266 }; 267 268 i2s@e0200000 { 269 compatible = "st,designware-i2s"; 270 reg = <0xe0200000 0x1000>; 271 interrupt-names = "play_irq", "record_irq"; 272 interrupts = <0 26 0x4 273 0 53 0x4>; 274 status = "disabled"; 275 }; 276 277 spi0: spi@e0100000 { 278 compatible = "arm,pl022", "arm,primecell"; 279 reg = <0xe0100000 0x1000>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 interrupts = <0 31 0x4>; 283 status = "disabled"; 284 dmas = <&dwdma0 0x2000 0 0 0>, /* 0x4 << 11 */ 285 <&dwdma0 0x0280 0 0 0>; /* 0x5 << 7 */ 286 dma-names = "tx", "rx"; 287 }; 288 289 rtc@e0580000 { 290 compatible = "st,spear600-rtc"; 291 reg = <0xe0580000 0x1000>; 292 interrupts = <0 36 0x4>; 293 status = "disabled"; 294 }; 295 296 serial@e0000000 { 297 compatible = "arm,pl011", "arm,primecell"; 298 reg = <0xe0000000 0x1000>; 299 interrupts = <0 35 0x4>; 300 status = "disabled"; 301 }; 302 303 adc@e0080000 { 304 compatible = "st,spear600-adc"; 305 reg = <0xe0080000 0x1000>; 306 interrupts = <0 12 0x4>; 307 status = "disabled"; 308 }; 309 310 timer@e0380000 { 311 compatible = "st,spear-timer"; 312 reg = <0xe0380000 0x400>; 313 interrupts = <0 37 0x4>; 314 }; 315 316 timer@ec800600 { 317 compatible = "arm,cortex-a9-twd-timer"; 318 reg = <0xec800600 0x20>; 319 interrupts = <1 13 0x4>; 320 status = "disabled"; 321 }; 322 323 wdt@ec800620 { 324 compatible = "arm,cortex-a9-twd-wdt"; 325 reg = <0xec800620 0x20>; 326 status = "disabled"; 327 }; 328 329 thermal@e07008c4 { 330 compatible = "st,thermal-spear1340"; 331 reg = <0xe07008c4 0x4>; 332 thermal_flags = <0x7000>; 333 }; 334 }; 335 }; 336}; 337