1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __T4_MSG_H 36 #define __T4_MSG_H 37 38 #include <linux/types.h> 39 40 enum { 41 CPL_PASS_OPEN_REQ = 0x1, 42 CPL_PASS_ACCEPT_RPL = 0x2, 43 CPL_ACT_OPEN_REQ = 0x3, 44 CPL_SET_TCB_FIELD = 0x5, 45 CPL_GET_TCB = 0x6, 46 CPL_CLOSE_CON_REQ = 0x8, 47 CPL_CLOSE_LISTSRV_REQ = 0x9, 48 CPL_ABORT_REQ = 0xA, 49 CPL_ABORT_RPL = 0xB, 50 CPL_RX_DATA_ACK = 0xD, 51 CPL_TX_PKT = 0xE, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_TID_RELEASE = 0x1A, 54 55 CPL_CLOSE_LISTSRV_RPL = 0x20, 56 CPL_L2T_WRITE_RPL = 0x23, 57 CPL_PASS_OPEN_RPL = 0x24, 58 CPL_ACT_OPEN_RPL = 0x25, 59 CPL_PEER_CLOSE = 0x26, 60 CPL_ABORT_REQ_RSS = 0x2B, 61 CPL_ABORT_RPL_RSS = 0x2D, 62 63 CPL_CLOSE_CON_RPL = 0x32, 64 CPL_ISCSI_HDR = 0x33, 65 CPL_RDMA_CQE = 0x35, 66 CPL_RDMA_CQE_READ_RSP = 0x36, 67 CPL_RDMA_CQE_ERR = 0x37, 68 CPL_RX_DATA = 0x39, 69 CPL_SET_TCB_RPL = 0x3A, 70 CPL_RX_PKT = 0x3B, 71 CPL_RX_DDP_COMPLETE = 0x3F, 72 73 CPL_ACT_ESTABLISH = 0x40, 74 CPL_PASS_ESTABLISH = 0x41, 75 CPL_RX_DATA_DDP = 0x42, 76 CPL_PASS_ACCEPT_REQ = 0x44, 77 CPL_TRACE_PKT_T5 = 0x48, 78 79 CPL_RDMA_READ_REQ = 0x60, 80 81 CPL_PASS_OPEN_REQ6 = 0x81, 82 CPL_ACT_OPEN_REQ6 = 0x83, 83 84 CPL_RDMA_TERMINATE = 0xA2, 85 CPL_RDMA_WRITE = 0xA4, 86 CPL_SGE_EGR_UPDATE = 0xA5, 87 88 CPL_TRACE_PKT = 0xB0, 89 90 CPL_FW4_MSG = 0xC0, 91 CPL_FW4_PLD = 0xC1, 92 CPL_FW4_ACK = 0xC3, 93 94 CPL_FW6_MSG = 0xE0, 95 CPL_FW6_PLD = 0xE1, 96 CPL_TX_PKT_LSO = 0xED, 97 CPL_TX_PKT_XT = 0xEE, 98 99 NUM_CPL_CMDS 100 }; 101 102 enum CPL_error { 103 CPL_ERR_NONE = 0, 104 CPL_ERR_TCAM_FULL = 3, 105 CPL_ERR_BAD_LENGTH = 15, 106 CPL_ERR_BAD_ROUTE = 18, 107 CPL_ERR_CONN_RESET = 20, 108 CPL_ERR_CONN_EXIST_SYNRECV = 21, 109 CPL_ERR_CONN_EXIST = 22, 110 CPL_ERR_ARP_MISS = 23, 111 CPL_ERR_BAD_SYN = 24, 112 CPL_ERR_CONN_TIMEDOUT = 30, 113 CPL_ERR_XMIT_TIMEDOUT = 31, 114 CPL_ERR_PERSIST_TIMEDOUT = 32, 115 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 116 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 117 CPL_ERR_RTX_NEG_ADVICE = 35, 118 CPL_ERR_PERSIST_NEG_ADVICE = 36, 119 CPL_ERR_ABORT_FAILED = 42, 120 CPL_ERR_IWARP_FLM = 50, 121 }; 122 123 enum { 124 ULP_MODE_NONE = 0, 125 ULP_MODE_ISCSI = 2, 126 ULP_MODE_RDMA = 4, 127 ULP_MODE_TCPDDP = 5, 128 ULP_MODE_FCOE = 6, 129 }; 130 131 enum { 132 ULP_CRC_HEADER = 1 << 0, 133 ULP_CRC_DATA = 1 << 1 134 }; 135 136 enum { 137 CPL_ABORT_SEND_RST = 0, 138 CPL_ABORT_NO_RST, 139 }; 140 141 enum { /* TX_PKT_XT checksum types */ 142 TX_CSUM_TCP = 0, 143 TX_CSUM_UDP = 1, 144 TX_CSUM_CRC16 = 4, 145 TX_CSUM_CRC32 = 5, 146 TX_CSUM_CRC32C = 6, 147 TX_CSUM_FCOE = 7, 148 TX_CSUM_TCPIP = 8, 149 TX_CSUM_UDPIP = 9, 150 TX_CSUM_TCPIP6 = 10, 151 TX_CSUM_UDPIP6 = 11, 152 TX_CSUM_IP = 12, 153 }; 154 155 union opcode_tid { 156 __be32 opcode_tid; 157 u8 opcode; 158 }; 159 160 #define CPL_OPCODE(x) ((x) << 24) 161 #define G_CPL_OPCODE(x) (((x) >> 24) & 0xFF) 162 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE(opcode) | (tid)) 163 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 164 #define GET_TID(cmd) (ntohl(OPCODE_TID(cmd)) & 0xFFFFFF) 165 166 /* partitioning of TID fields that also carry a queue id */ 167 #define GET_TID_TID(x) ((x) & 0x3fff) 168 #define GET_TID_QID(x) (((x) >> 14) & 0x3ff) 169 #define TID_QID(x) ((x) << 14) 170 171 struct rss_header { 172 u8 opcode; 173 #if defined(__LITTLE_ENDIAN_BITFIELD) 174 u8 channel:2; 175 u8 filter_hit:1; 176 u8 filter_tid:1; 177 u8 hash_type:2; 178 u8 ipv6:1; 179 u8 send2fw:1; 180 #else 181 u8 send2fw:1; 182 u8 ipv6:1; 183 u8 hash_type:2; 184 u8 filter_tid:1; 185 u8 filter_hit:1; 186 u8 channel:2; 187 #endif 188 __be16 qid; 189 __be32 hash_val; 190 }; 191 192 struct work_request_hdr { 193 __be32 wr_hi; 194 __be32 wr_mid; 195 __be64 wr_lo; 196 }; 197 198 /* wr_hi fields */ 199 #define S_WR_OP 24 200 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 201 202 #define WR_HDR struct work_request_hdr wr 203 204 /* option 0 fields */ 205 #define S_MSS_IDX 60 206 #define M_MSS_IDX 0xF 207 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 208 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 209 210 /* option 2 fields */ 211 #define S_RSS_QUEUE 0 212 #define M_RSS_QUEUE 0x3FF 213 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 214 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 215 216 struct cpl_pass_open_req { 217 WR_HDR; 218 union opcode_tid ot; 219 __be16 local_port; 220 __be16 peer_port; 221 __be32 local_ip; 222 __be32 peer_ip; 223 __be64 opt0; 224 #define TX_CHAN(x) ((x) << 2) 225 #define NO_CONG(x) ((x) << 4) 226 #define DELACK(x) ((x) << 5) 227 #define ULP_MODE(x) ((x) << 8) 228 #define RCV_BUFSIZ(x) ((x) << 12) 229 #define DSCP(x) ((x) << 22) 230 #define SMAC_SEL(x) ((u64)(x) << 28) 231 #define L2T_IDX(x) ((u64)(x) << 36) 232 #define TCAM_BYPASS(x) ((u64)(x) << 48) 233 #define NAGLE(x) ((u64)(x) << 49) 234 #define WND_SCALE(x) ((u64)(x) << 50) 235 #define KEEP_ALIVE(x) ((u64)(x) << 54) 236 #define MSS_IDX(x) ((u64)(x) << 60) 237 __be64 opt1; 238 #define SYN_RSS_ENABLE (1 << 0) 239 #define SYN_RSS_QUEUE(x) ((x) << 2) 240 #define CONN_POLICY_ASK (1 << 22) 241 }; 242 243 struct cpl_pass_open_req6 { 244 WR_HDR; 245 union opcode_tid ot; 246 __be16 local_port; 247 __be16 peer_port; 248 __be64 local_ip_hi; 249 __be64 local_ip_lo; 250 __be64 peer_ip_hi; 251 __be64 peer_ip_lo; 252 __be64 opt0; 253 __be64 opt1; 254 }; 255 256 struct cpl_pass_open_rpl { 257 union opcode_tid ot; 258 u8 rsvd[3]; 259 u8 status; 260 }; 261 262 struct cpl_pass_accept_rpl { 263 WR_HDR; 264 union opcode_tid ot; 265 __be32 opt2; 266 #define RSS_QUEUE(x) ((x) << 0) 267 #define RSS_QUEUE_VALID (1 << 10) 268 #define RX_COALESCE_VALID(x) ((x) << 11) 269 #define RX_COALESCE(x) ((x) << 12) 270 #define PACE(x) ((x) << 16) 271 #define TX_QUEUE(x) ((x) << 23) 272 #define RX_CHANNEL(x) ((x) << 26) 273 #define CCTRL_ECN(x) ((x) << 27) 274 #define WND_SCALE_EN(x) ((x) << 28) 275 #define TSTAMPS_EN(x) ((x) << 29) 276 #define SACK_EN(x) ((x) << 30) 277 __be64 opt0; 278 }; 279 280 struct cpl_act_open_req { 281 WR_HDR; 282 union opcode_tid ot; 283 __be16 local_port; 284 __be16 peer_port; 285 __be32 local_ip; 286 __be32 peer_ip; 287 __be64 opt0; 288 __be32 params; 289 __be32 opt2; 290 }; 291 292 #define S_FILTER_TUPLE 24 293 #define M_FILTER_TUPLE 0xFFFFFFFFFF 294 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) 295 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) 296 struct cpl_t5_act_open_req { 297 WR_HDR; 298 union opcode_tid ot; 299 __be16 local_port; 300 __be16 peer_port; 301 __be32 local_ip; 302 __be32 peer_ip; 303 __be64 opt0; 304 __be32 rsvd; 305 __be32 opt2; 306 __be64 params; 307 }; 308 309 struct cpl_act_open_req6 { 310 WR_HDR; 311 union opcode_tid ot; 312 __be16 local_port; 313 __be16 peer_port; 314 __be64 local_ip_hi; 315 __be64 local_ip_lo; 316 __be64 peer_ip_hi; 317 __be64 peer_ip_lo; 318 __be64 opt0; 319 __be32 params; 320 __be32 opt2; 321 }; 322 323 struct cpl_act_open_rpl { 324 union opcode_tid ot; 325 __be32 atid_status; 326 #define GET_AOPEN_STATUS(x) ((x) & 0xff) 327 #define GET_AOPEN_ATID(x) (((x) >> 8) & 0xffffff) 328 }; 329 330 struct cpl_pass_establish { 331 union opcode_tid ot; 332 __be32 rsvd; 333 __be32 tos_stid; 334 #define PASS_OPEN_TID(x) ((x) << 0) 335 #define PASS_OPEN_TOS(x) ((x) << 24) 336 #define GET_PASS_OPEN_TID(x) (((x) >> 0) & 0xFFFFFF) 337 #define GET_POPEN_TID(x) ((x) & 0xffffff) 338 #define GET_POPEN_TOS(x) (((x) >> 24) & 0xff) 339 __be16 mac_idx; 340 __be16 tcp_opt; 341 #define GET_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 342 #define GET_TCPOPT_SACK(x) (((x) >> 6) & 1) 343 #define GET_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 344 #define GET_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 345 #define GET_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 346 __be32 snd_isn; 347 __be32 rcv_isn; 348 }; 349 350 struct cpl_act_establish { 351 union opcode_tid ot; 352 __be32 rsvd; 353 __be32 tos_atid; 354 __be16 mac_idx; 355 __be16 tcp_opt; 356 __be32 snd_isn; 357 __be32 rcv_isn; 358 }; 359 360 struct cpl_get_tcb { 361 WR_HDR; 362 union opcode_tid ot; 363 __be16 reply_ctrl; 364 #define QUEUENO(x) ((x) << 0) 365 #define REPLY_CHAN(x) ((x) << 14) 366 #define NO_REPLY(x) ((x) << 15) 367 __be16 cookie; 368 }; 369 370 struct cpl_set_tcb_field { 371 WR_HDR; 372 union opcode_tid ot; 373 __be16 reply_ctrl; 374 __be16 word_cookie; 375 #define TCB_WORD(x) ((x) << 0) 376 #define TCB_COOKIE(x) ((x) << 5) 377 #define GET_TCB_COOKIE(x) (((x) >> 5) & 7) 378 __be64 mask; 379 __be64 val; 380 }; 381 382 struct cpl_set_tcb_rpl { 383 union opcode_tid ot; 384 __be16 rsvd; 385 u8 cookie; 386 u8 status; 387 __be64 oldval; 388 }; 389 390 struct cpl_close_con_req { 391 WR_HDR; 392 union opcode_tid ot; 393 __be32 rsvd; 394 }; 395 396 struct cpl_close_con_rpl { 397 union opcode_tid ot; 398 u8 rsvd[3]; 399 u8 status; 400 __be32 snd_nxt; 401 __be32 rcv_nxt; 402 }; 403 404 struct cpl_close_listsvr_req { 405 WR_HDR; 406 union opcode_tid ot; 407 __be16 reply_ctrl; 408 #define LISTSVR_IPV6 (1 << 14) 409 __be16 rsvd; 410 }; 411 412 struct cpl_close_listsvr_rpl { 413 union opcode_tid ot; 414 u8 rsvd[3]; 415 u8 status; 416 }; 417 418 struct cpl_abort_req_rss { 419 union opcode_tid ot; 420 u8 rsvd[3]; 421 u8 status; 422 }; 423 424 struct cpl_abort_req { 425 WR_HDR; 426 union opcode_tid ot; 427 __be32 rsvd0; 428 u8 rsvd1; 429 u8 cmd; 430 u8 rsvd2[6]; 431 }; 432 433 struct cpl_abort_rpl_rss { 434 union opcode_tid ot; 435 u8 rsvd[3]; 436 u8 status; 437 }; 438 439 struct cpl_abort_rpl { 440 WR_HDR; 441 union opcode_tid ot; 442 __be32 rsvd0; 443 u8 rsvd1; 444 u8 cmd; 445 u8 rsvd2[6]; 446 }; 447 448 struct cpl_peer_close { 449 union opcode_tid ot; 450 __be32 rcv_nxt; 451 }; 452 453 struct cpl_tid_release { 454 WR_HDR; 455 union opcode_tid ot; 456 __be32 rsvd; 457 }; 458 459 struct cpl_tx_pkt_core { 460 __be32 ctrl0; 461 #define TXPKT_VF(x) ((x) << 0) 462 #define TXPKT_PF(x) ((x) << 8) 463 #define TXPKT_VF_VLD (1 << 11) 464 #define TXPKT_OVLAN_IDX(x) ((x) << 12) 465 #define TXPKT_INTF(x) ((x) << 16) 466 #define TXPKT_INS_OVLAN (1 << 21) 467 #define TXPKT_OPCODE(x) ((x) << 24) 468 __be16 pack; 469 __be16 len; 470 __be64 ctrl1; 471 #define TXPKT_CSUM_END(x) ((x) << 12) 472 #define TXPKT_CSUM_START(x) ((x) << 20) 473 #define TXPKT_IPHDR_LEN(x) ((u64)(x) << 20) 474 #define TXPKT_CSUM_LOC(x) ((u64)(x) << 30) 475 #define TXPKT_ETHHDR_LEN(x) ((u64)(x) << 34) 476 #define TXPKT_CSUM_TYPE(x) ((u64)(x) << 40) 477 #define TXPKT_VLAN(x) ((u64)(x) << 44) 478 #define TXPKT_VLAN_VLD (1ULL << 60) 479 #define TXPKT_IPCSUM_DIS (1ULL << 62) 480 #define TXPKT_L4CSUM_DIS (1ULL << 63) 481 }; 482 483 struct cpl_tx_pkt { 484 WR_HDR; 485 struct cpl_tx_pkt_core c; 486 }; 487 488 #define cpl_tx_pkt_xt cpl_tx_pkt 489 490 struct cpl_tx_pkt_lso_core { 491 __be32 lso_ctrl; 492 #define LSO_TCPHDR_LEN(x) ((x) << 0) 493 #define LSO_IPHDR_LEN(x) ((x) << 4) 494 #define LSO_ETHHDR_LEN(x) ((x) << 16) 495 #define LSO_IPV6(x) ((x) << 20) 496 #define LSO_LAST_SLICE (1 << 22) 497 #define LSO_FIRST_SLICE (1 << 23) 498 #define LSO_OPCODE(x) ((x) << 24) 499 __be16 ipid_ofst; 500 __be16 mss; 501 __be32 seqno_offset; 502 __be32 len; 503 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 504 }; 505 506 struct cpl_tx_pkt_lso { 507 WR_HDR; 508 struct cpl_tx_pkt_lso_core c; 509 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 510 }; 511 512 struct cpl_iscsi_hdr { 513 union opcode_tid ot; 514 __be16 pdu_len_ddp; 515 #define ISCSI_PDU_LEN(x) ((x) & 0x7FFF) 516 #define ISCSI_DDP (1 << 15) 517 __be16 len; 518 __be32 seq; 519 __be16 urg; 520 u8 rsvd; 521 u8 status; 522 }; 523 524 struct cpl_rx_data { 525 union opcode_tid ot; 526 __be16 rsvd; 527 __be16 len; 528 __be32 seq; 529 __be16 urg; 530 #if defined(__LITTLE_ENDIAN_BITFIELD) 531 u8 dack_mode:2; 532 u8 psh:1; 533 u8 heartbeat:1; 534 u8 ddp_off:1; 535 u8 :3; 536 #else 537 u8 :3; 538 u8 ddp_off:1; 539 u8 heartbeat:1; 540 u8 psh:1; 541 u8 dack_mode:2; 542 #endif 543 u8 status; 544 }; 545 546 struct cpl_rx_data_ack { 547 WR_HDR; 548 union opcode_tid ot; 549 __be32 credit_dack; 550 #define RX_CREDITS(x) ((x) << 0) 551 #define RX_FORCE_ACK(x) ((x) << 28) 552 }; 553 554 struct cpl_rx_pkt { 555 struct rss_header rsshdr; 556 u8 opcode; 557 #if defined(__LITTLE_ENDIAN_BITFIELD) 558 u8 iff:4; 559 u8 csum_calc:1; 560 u8 ipmi_pkt:1; 561 u8 vlan_ex:1; 562 u8 ip_frag:1; 563 #else 564 u8 ip_frag:1; 565 u8 vlan_ex:1; 566 u8 ipmi_pkt:1; 567 u8 csum_calc:1; 568 u8 iff:4; 569 #endif 570 __be16 csum; 571 __be16 vlan; 572 __be16 len; 573 __be32 l2info; 574 #define RXF_UDP (1 << 22) 575 #define RXF_TCP (1 << 23) 576 #define RXF_IP (1 << 24) 577 #define RXF_IP6 (1 << 25) 578 __be16 hdr_len; 579 __be16 err_vec; 580 }; 581 582 /* rx_pkt.l2info fields */ 583 #define S_RX_ETHHDR_LEN 0 584 #define M_RX_ETHHDR_LEN 0x1F 585 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 586 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 587 588 #define S_RX_T5_ETHHDR_LEN 0 589 #define M_RX_T5_ETHHDR_LEN 0x3F 590 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 591 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 592 593 #define S_RX_MACIDX 8 594 #define M_RX_MACIDX 0x1FF 595 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 596 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 597 598 #define S_RXF_SYN 21 599 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 600 #define F_RXF_SYN V_RXF_SYN(1U) 601 602 #define S_RX_CHAN 28 603 #define M_RX_CHAN 0xF 604 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 605 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 606 607 /* rx_pkt.hdr_len fields */ 608 #define S_RX_TCPHDR_LEN 0 609 #define M_RX_TCPHDR_LEN 0x3F 610 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 611 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 612 613 #define S_RX_IPHDR_LEN 6 614 #define M_RX_IPHDR_LEN 0x3FF 615 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 616 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 617 618 struct cpl_trace_pkt { 619 u8 opcode; 620 u8 intf; 621 #if defined(__LITTLE_ENDIAN_BITFIELD) 622 u8 runt:4; 623 u8 filter_hit:4; 624 u8 :6; 625 u8 err:1; 626 u8 trunc:1; 627 #else 628 u8 filter_hit:4; 629 u8 runt:4; 630 u8 trunc:1; 631 u8 err:1; 632 u8 :6; 633 #endif 634 __be16 rsvd; 635 __be16 len; 636 __be64 tstamp; 637 }; 638 639 struct cpl_t5_trace_pkt { 640 __u8 opcode; 641 __u8 intf; 642 #if defined(__LITTLE_ENDIAN_BITFIELD) 643 __u8 runt:4; 644 __u8 filter_hit:4; 645 __u8:6; 646 __u8 err:1; 647 __u8 trunc:1; 648 #else 649 __u8 filter_hit:4; 650 __u8 runt:4; 651 __u8 trunc:1; 652 __u8 err:1; 653 __u8:6; 654 #endif 655 __be16 rsvd; 656 __be16 len; 657 __be64 tstamp; 658 __be64 rsvd1; 659 }; 660 661 struct cpl_l2t_write_req { 662 WR_HDR; 663 union opcode_tid ot; 664 __be16 params; 665 #define L2T_W_INFO(x) ((x) << 2) 666 #define L2T_W_PORT(x) ((x) << 8) 667 #define L2T_W_NOREPLY(x) ((x) << 15) 668 __be16 l2t_idx; 669 __be16 vlan; 670 u8 dst_mac[6]; 671 }; 672 673 struct cpl_l2t_write_rpl { 674 union opcode_tid ot; 675 u8 status; 676 u8 rsvd[3]; 677 }; 678 679 struct cpl_rdma_terminate { 680 union opcode_tid ot; 681 __be16 rsvd; 682 __be16 len; 683 }; 684 685 struct cpl_sge_egr_update { 686 __be32 opcode_qid; 687 #define EGR_QID(x) ((x) & 0x1FFFF) 688 __be16 cidx; 689 __be16 pidx; 690 }; 691 692 /* cpl_fw*.type values */ 693 enum { 694 FW_TYPE_CMD_RPL = 0, 695 FW_TYPE_WR_RPL = 1, 696 FW_TYPE_CQE = 2, 697 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 698 FW_TYPE_RSSCPL = 4, 699 }; 700 701 struct cpl_fw4_pld { 702 u8 opcode; 703 u8 rsvd0[3]; 704 u8 type; 705 u8 rsvd1; 706 __be16 len; 707 __be64 data; 708 __be64 rsvd2; 709 }; 710 711 struct cpl_fw6_pld { 712 u8 opcode; 713 u8 rsvd[5]; 714 __be16 len; 715 __be64 data[4]; 716 }; 717 718 struct cpl_fw4_msg { 719 u8 opcode; 720 u8 type; 721 __be16 rsvd0; 722 __be32 rsvd1; 723 __be64 data[2]; 724 }; 725 726 struct cpl_fw4_ack { 727 union opcode_tid ot; 728 u8 credits; 729 u8 rsvd0[2]; 730 u8 seq_vld; 731 __be32 snd_nxt; 732 __be32 snd_una; 733 __be64 rsvd1; 734 }; 735 736 struct cpl_fw6_msg { 737 u8 opcode; 738 u8 type; 739 __be16 rsvd0; 740 __be32 rsvd1; 741 __be64 data[4]; 742 }; 743 744 /* cpl_fw6_msg.type values */ 745 enum { 746 FW6_TYPE_CMD_RPL = 0, 747 FW6_TYPE_WR_RPL = 1, 748 FW6_TYPE_CQE = 2, 749 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, 750 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 751 }; 752 753 struct cpl_fw6_msg_ofld_connection_wr_rpl { 754 __u64 cookie; 755 __be32 tid; /* or atid in case of active failure */ 756 __u8 t_state; 757 __u8 retval; 758 __u8 rsvd[2]; 759 }; 760 761 enum { 762 ULP_TX_MEM_READ = 2, 763 ULP_TX_MEM_WRITE = 3, 764 ULP_TX_PKT = 4 765 }; 766 767 enum { 768 ULP_TX_SC_NOOP = 0x80, 769 ULP_TX_SC_IMM = 0x81, 770 ULP_TX_SC_DSGL = 0x82, 771 ULP_TX_SC_ISGL = 0x83 772 }; 773 774 struct ulptx_sge_pair { 775 __be32 len[2]; 776 __be64 addr[2]; 777 }; 778 779 struct ulptx_sgl { 780 __be32 cmd_nsge; 781 #define ULPTX_CMD(x) ((x) << 24) 782 #define ULPTX_NSGE(x) ((x) << 0) 783 #define ULPTX_MORE (1U << 23) 784 __be32 len0; 785 __be64 addr0; 786 struct ulptx_sge_pair sge[0]; 787 }; 788 789 struct ulp_mem_io { 790 WR_HDR; 791 __be32 cmd; 792 #define ULP_MEMIO_ORDER(x) ((x) << 23) 793 __be32 len16; /* command length */ 794 __be32 dlen; /* data length in 32-byte units */ 795 #define ULP_MEMIO_DATA_LEN(x) ((x) << 0) 796 __be32 lock_addr; 797 #define ULP_MEMIO_ADDR(x) ((x) << 0) 798 #define ULP_MEMIO_LOCK(x) ((x) << 31) 799 }; 800 801 #define S_T5_ULP_MEMIO_IMM 23 802 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 803 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 804 805 #define S_T5_ULP_MEMIO_ORDER 22 806 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 807 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 808 809 #endif /* __T4_MSG_H */ 810