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1 /*
2  * DO NOT EDIT THIS FILE
3  * This file is under version control at
4  *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
5  * and can be replaced with that version at any time
6  * DO NOT EDIT THIS FILE
7  *
8  * Copyright 2004-2011 Analog Devices Inc.
9  * Licensed under the Clear BSD license.
10  */
11 
12 /* This file should be up to date with:
13  *  - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
14  */
15 
16 #ifndef _MACH_ANOMALY_H_
17 #define _MACH_ANOMALY_H_
18 
19 /* We do not support 0.1 or 0.2 silicon - sorry */
20 #if __SILICON_REVISION__ < 3
21 # error will not work on BF533 silicon version 0.0, 0.1, or 0.2
22 #endif
23 
24 #if defined(__ADSPBF531__)
25 # define ANOMALY_BF531 1
26 #else
27 # define ANOMALY_BF531 0
28 #endif
29 #if defined(__ADSPBF532__)
30 # define ANOMALY_BF532 1
31 #else
32 # define ANOMALY_BF532 0
33 #endif
34 #if defined(__ADSPBF533__)
35 # define ANOMALY_BF533 1
36 #else
37 # define ANOMALY_BF533 0
38 #endif
39 
40 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
41 #define ANOMALY_05000074 (1)
42 /* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
43 #define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
44 /* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
45 #define ANOMALY_05000105 (__SILICON_REVISION__ > 2)
46 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
47 #define ANOMALY_05000119 (1)
48 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
49 #define ANOMALY_05000122 (1)
50 /* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
51 #define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
52 /* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
53 #define ANOMALY_05000166 (1)
54 /* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
55 #define ANOMALY_05000167 (1)
56 /* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
57 #define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
58 /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
59 #define ANOMALY_05000180 (1)
60 /* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
61 #define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
62 /* False Protection Exceptions when Speculative Fetch Is Cancelled */
63 #define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
64 /* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
65 #define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
66 /* Restarting SPORT in Specific Modes May Cause Data Corruption */
67 #define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
68 /* Failing MMR Accesses when Preceding Memory Read Stalls */
69 #define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
70 /* Current DMA Address Shows Wrong Value During Carry Fix */
71 #define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
72 /* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
73 #define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4)
74 /* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
75 #define ANOMALY_05000201 (__SILICON_REVISION__ == 3)
76 /* Possible Infinite Stall with Specific Dual-DAG Situation */
77 #define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
78 /* Specific Sequence That Can Cause DMA Error or DMA Stopping */
79 #define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
80 /* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
81 #define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
82 /* Recovery from "Brown-Out" Condition */
83 #define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
84 /* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
85 #define ANOMALY_05000208 (1)
86 /* Speed Path in Computational Unit Affects Certain Instructions */
87 #define ANOMALY_05000209 (__SILICON_REVISION__ < 4)
88 /* UART TX Interrupt Masked Erroneously */
89 #define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
90 /* NMI Event at Boot Time Results in Unpredictable State */
91 #define ANOMALY_05000219 (1)
92 /* Incorrect Pulse-Width of UART Start Bit */
93 #define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
94 /* Scratchpad Memory Bank Reads May Return Incorrect Data */
95 #define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
96 /* SPI Slave Boot Mode Modifies Registers from Reset Value */
97 #define ANOMALY_05000229 (1)
98 /* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
99 #define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
100 /* UART STB Bit Incorrectly Affects Receiver Setting */
101 #define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
102 /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
103 #define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
104 /* Incorrect Revision Number in DSPID Register */
105 #define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
106 /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
107 #define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
108 /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
109 #define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
110 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
111 #define ANOMALY_05000245 (1)
112 /* Data CPLBs Should Prevent False Hardware Errors */
113 #define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
114 /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
115 #define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
116 /* Maximum External Clock Speed for Timers */
117 #define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
118 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
119 #define ANOMALY_05000254 (__SILICON_REVISION__ > 4)
120 /* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
121 #define ANOMALY_05000255 (__SILICON_REVISION__ < 5)
122 /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
123 #define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
124 /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
125 #define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
126 /* ICPLB_STATUS MMR Register May Be Corrupted */
127 #define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
128 /* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
129 #define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
130 /* Stores To Data Cache May Be Lost */
131 #define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
132 /* Hardware Loop Corrupted When Taking an ICPLB Exception */
133 #define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
134 /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
135 #define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
136 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
137 #define ANOMALY_05000265 (1)
138 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
139 #define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
140 /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
141 #define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
142 /* Spontaneous Reset of Internal Voltage Regulator */
143 #define ANOMALY_05000271 (__SILICON_REVISION__ == 3)
144 /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
145 #define ANOMALY_05000272 (1)
146 /* Writes to Synchronous SDRAM Memory May Be Lost */
147 #define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
148 /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
149 #define ANOMALY_05000276 (1)
150 /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
151 #define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
152 /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
153 #define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
154 /* False Hardware Error when ISR Context Is Not Restored */
155 #define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
156 /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
157 #define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
158 /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
159 #define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
160 /* SPORTs May Receive Bad Data If FIFOs Fill Up */
161 #define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
162 /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
163 #define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
164 /* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
165 #define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
166 /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
167 #define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
168 /* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */
169 #define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
170 /* SCKELOW Bit Does Not Maintain State Through Hibernate */
171 #define ANOMALY_05000307 (1)	/* note: brokenness is noted in documentation, not anomaly sheet */
172 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
173 #define ANOMALY_05000310 (1)
174 /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
175 #define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
176 /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
177 #define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
178 /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
179 #define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
180 /* Killed System MMR Write Completes Erroneously on Next System MMR Access */
181 #define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
182 /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
183 #define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
184 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
185 #define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
186 /* UART Break Signal Issues */
187 #define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
188 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
189 #define ANOMALY_05000366 (1)
190 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
191 #define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
192 /* PPI Does Not Start Properly In Specific Mode */
193 #define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
194 /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
195 #define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
196 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
197 #define ANOMALY_05000403 (1)
198 /* Speculative Fetches Can Cause Undesired External FIFO Operations */
199 #define ANOMALY_05000416 (1)
200 /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
201 #define ANOMALY_05000425 (1)
202 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
203 #define ANOMALY_05000426 (1)
204 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
205 #define ANOMALY_05000443 (1)
206 /* False Hardware Error when RETI Points to Invalid Memory */
207 #define ANOMALY_05000461 (1)
208 /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
209 #define ANOMALY_05000462 (1)
210 /* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
211 #define ANOMALY_05000471 (1)
212 /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
213 #define ANOMALY_05000473 (1)
214 /* Possible Lockup Condition when Modifying PLL from External Memory */
215 #define ANOMALY_05000475 (1)
216 /* TESTSET Instruction Cannot Be Interrupted */
217 #define ANOMALY_05000477 (1)
218 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
219 #define ANOMALY_05000481 (1)
220 /* PLL May Latch Incorrect Values Coming Out of Reset */
221 #define ANOMALY_05000489 (1)
222 /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
223 #define ANOMALY_05000491 (1)
224 /* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
225 #define ANOMALY_05000494 (1)
226 /* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
227 #define ANOMALY_05000501 (1)
228 
229 /*
230  * These anomalies have been "phased" out of analog.com anomaly sheets and are
231  * here to show running on older silicon just isn't feasible.
232  */
233 
234 /* Internal voltage regulator can't be modified via register writes */
235 #define ANOMALY_05000066 (__SILICON_REVISION__ < 2)
236 /* Watchpoints (Hardware Breakpoints) are not supported */
237 #define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
238 /* SDRAM PSSE bit cannot be set again after SDRAM Powerup */
239 #define ANOMALY_05000070 (__SILICON_REVISION__ < 2)
240 /* Writing FIO_DIR can corrupt a programmable flag's data */
241 #define ANOMALY_05000079 (__SILICON_REVISION__ < 2)
242 /* Timer Auto-Baud Mode requires the UART clock to be enabled. */
243 #define ANOMALY_05000086 (__SILICON_REVISION__ < 2)
244 /* Internal Clocking Modes on SPORT0 not supported */
245 #define ANOMALY_05000088 (__SILICON_REVISION__ < 2)
246 /* Internal voltage regulator does not wake up from an RTC wakeup */
247 #define ANOMALY_05000092 (__SILICON_REVISION__ < 2)
248 /* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */
249 #define ANOMALY_05000093 (__SILICON_REVISION__ < 2)
250 /* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */
251 #define ANOMALY_05000095 (__SILICON_REVISION__ < 2)
252 /* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */
253 #define ANOMALY_05000096 (__SILICON_REVISION__ < 2)
254 /* Performance Monitor 0 and 1 are swapped when monitoring memory events */
255 #define ANOMALY_05000097 (__SILICON_REVISION__ < 2)
256 /* 32-bit SPORT DMA will be word reversed */
257 #define ANOMALY_05000098 (__SILICON_REVISION__ < 2)
258 /* Incorrect status in the UART_IIR register */
259 #define ANOMALY_05000100 (__SILICON_REVISION__ < 2)
260 /* Reading X_MODIFY or Y_MODIFY while DMA channel is active */
261 #define ANOMALY_05000101 (__SILICON_REVISION__ < 2)
262 /* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */
263 #define ANOMALY_05000102 (__SILICON_REVISION__ < 2)
264 /* Incorrect Value Written to the Cycle Counters */
265 #define ANOMALY_05000103 (__SILICON_REVISION__ < 2)
266 /* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */
267 #define ANOMALY_05000104 (__SILICON_REVISION__ < 2)
268 /* Programmable Flag (PF3) functionality not supported in all PPI modes */
269 #define ANOMALY_05000106 (__SILICON_REVISION__ < 2)
270 /* Data store can be lost when targeting a cache line fill */
271 #define ANOMALY_05000107 (__SILICON_REVISION__ < 2)
272 /* Reserved Bits in SYSCFG Register Not Set at Power-On */
273 #define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
274 /* Infinite Core Stall */
275 #define ANOMALY_05000114 (__SILICON_REVISION__ < 2)
276 /* PPI_FSx may glitch when generated by the on chip Timers. */
277 #define ANOMALY_05000115 (__SILICON_REVISION__ < 2)
278 /* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
279 #define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
280 /* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */
281 #define ANOMALY_05000117 (__SILICON_REVISION__ < 2)
282 /* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */
283 #define ANOMALY_05000118 (__SILICON_REVISION__ < 2)
284 /* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */
285 #define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
286 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
287 #define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
288 /* Erroneous Exception when Enabling Cache */
289 #define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
290 /* SPI clock polarity and phase bits incorrect during booting */
291 #define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
292 /* DMEM_CONTROL<12> Is Not Set on Reset */
293 #define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
294 /* SPI boot will not complete if there is a zero fill block in the loader file */
295 #define ANOMALY_05000138 (__SILICON_REVISION__ == 2)
296 /* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */
297 #define ANOMALY_05000139 (__SILICON_REVISION__ < 2)
298 /* Allowing the SPORT RX FIFO to fill will cause an overflow */
299 #define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
300 /* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
301 #define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
302 /* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
303 #define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
304 /* A read from external memory may return a wrong value with data cache enabled */
305 #define ANOMALY_05000143 (__SILICON_REVISION__ < 3)
306 /* DMA and TESTSET conflict when both are accessing external memory */
307 #define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
308 /* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
309 #define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
310 /* MDMA may lose the first few words of a descriptor chain */
311 #define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
312 /* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
313 #define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
314 /* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */
315 #define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
316 /* Frame Delay in SPORT Multichannel Mode */
317 #define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
318 /* SPORT TFS signal stays active in multichannel mode outside of valid channels */
319 #define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
320 /* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
321 #define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
322 /* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
323 #define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
324 /* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
325 #define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
326 /* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
327 #define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
328 /* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
329 #define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
330 /* DMA vs Core accesses to external memory */
331 #define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
332 /* Cache Fill Buffer Data lost */
333 #define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
334 /* Overlapping Sequencer and Memory Stalls */
335 #define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
336 /* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
337 #define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
338 /* Disabling the PPI Resets the PPI Configuration Registers */
339 #define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
340 /* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
341 #define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
342 /* PPI does not invert the Driving PPICLK edge in Transmit Modes */
343 #define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
344 /* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */
345 #define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
346 /* Internal Voltage Regulator may not start up */
347 #define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
348 
349 /* Anomalies that don't exist on this proc */
350 #define ANOMALY_05000120 (0)
351 #define ANOMALY_05000149 (0)
352 #define ANOMALY_05000171 (0)
353 #define ANOMALY_05000182 (0)
354 #define ANOMALY_05000220 (0)
355 #define ANOMALY_05000248 (0)
356 #define ANOMALY_05000266 (0)
357 #define ANOMALY_05000274 (0)
358 #define ANOMALY_05000287 (0)
359 #define ANOMALY_05000323 (0)
360 #define ANOMALY_05000353 (1)
361 #define ANOMALY_05000362 (1)
362 #define ANOMALY_05000364 (0)
363 #define ANOMALY_05000380 (0)
364 #define ANOMALY_05000383 (0)
365 #define ANOMALY_05000386 (1)
366 #define ANOMALY_05000389 (0)
367 #define ANOMALY_05000412 (0)
368 #define ANOMALY_05000430 (0)
369 #define ANOMALY_05000432 (0)
370 #define ANOMALY_05000435 (0)
371 #define ANOMALY_05000440 (0)
372 #define ANOMALY_05000447 (0)
373 #define ANOMALY_05000448 (0)
374 #define ANOMALY_05000456 (0)
375 #define ANOMALY_05000450 (0)
376 #define ANOMALY_05000465 (0)
377 #define ANOMALY_05000467 (0)
378 #define ANOMALY_05000474 (0)
379 #define ANOMALY_05000480 (0)
380 #define ANOMALY_05000485 (0)
381 #define ANOMALY_16000030 (0)
382 
383 #endif
384