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Searched refs:ASID (Results 1 – 13 of 13) sorted by relevance

/arch/arm/include/asm/
Dmmu.h17 #define ASID(mm) ((mm)->context.id.counter & ~ASID_MASK) macro
19 #define ASID(mm) (0) macro
Dtlbflush.h344 const int asid = ASID(mm); in local_flush_tlb_mm()
378 uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); in local_flush_tlb_page()
/arch/m32r/mm/
Dmmu.S37 ld r0, @(MDEVP_offset, r3) ; r0: PFN + ASID (MDEVP reg.)
44 ;; r0: PFN + ASID (MDEVP reg.)
47 ;; r0: PFN + ASID
73 ;; r0: MDEVP reg. (included ASID)
76 ;; r0: PFN + ASID
84 or r0, r1 ; r0: PFN + ASID
104 ;; r0: PFN + ASID
109 ;; r0: PFN + ASID
131 ;; r0: PFN + ASID
135 ;; r0: PFN + ASID
[all …]
/arch/arm64/include/asm/
Dtlbflush.h83 unsigned long asid = (unsigned long)ASID(mm) << 48; in flush_tlb_mm()
94 ((unsigned long)ASID(vma->vm_mm) << 48); in flush_tlb_page()
Dmmu.h28 #define ASID(mm) ((mm)->context.id & 0xffff) macro
/arch/avr32/mach-at32ap/
Dpm.c58 tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi)); in avr32_pm_map_sram()
85 tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi)); in avr32_pm_unmap_sram()
/arch/arm/mm/
Dtlb-v7.S41 asid r3, r3 @ mask ASID
50 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
79 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable)
Dtlb-v6.S42 asid r3, r3 @ mask ASID
Dproc-v7-3level.S52 mov r3, r3, lsl #(48 - 32) @ ASID
DKconfig566 This indicates whether the CPU has the ASID register; used to
/arch/arc/mm/
Dtlbex.S73 ; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid
75 ; we use the MMU PID Reg to get current ASID.
76 ; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble.
84 ; make sure h/w ASID is same as s/w ASID
94 ; Error if H/w and S/w ASID don't match, but NOT if in kernel mode
232 ; VERIFY if the ASID in MMU-PID Reg is same as
/arch/avr32/mm/
Dtlb.c38 SYSREG_BFEXT(ASID, tlbehi), in show_dtlb_entry()
73 tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi)); in update_dtlb()
337 SYSREG_BFEXT(ASID, tlbehi), in tlb_show()
/arch/arm/
DKconfig1229 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1233 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1238 entries regardless of the ASID.
1292 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1297 which starts prior to an ASID switch but completes afterwards. This
1299 the new ASID. This workaround places two dsb instructions in the mm
1300 switching code so that no page table walks can cross the ASID switch.
1368 which sends an IPI to the CPUs that are running the same ASID