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Searched refs:A_SCD_TRACE_SEQUENCE_5 (Results 1 – 2 of 2) sorted by relevance

/arch/mips/sibyte/common/
Dsb_tbprof.c352 __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5)); in sbprof_zbprof_start()
/arch/mips/include/asm/sibyte/
Dsb1250_regs.h800 #define A_SCD_TRACE_SEQUENCE_5 0x0010020A88 macro