Home
last modified time | relevance | path

Searched refs:CCM_CSCR (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-imx/
Dclk-imx1.c32 #define CCM_CSCR IO_ADDR_CCM(0x0) macro
60 clk[clk16m] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); in mx1_clocks_init()
62 clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, in mx1_clocks_init()
66 clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1); in mx1_clocks_init()
67 clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 15, 1); in mx1_clocks_init()
68 clk[hclk] = imx_clk_divider("hclk", "spll", CCM_CSCR, 10, 4); in mx1_clocks_init()
69 clk[clk48m] = imx_clk_divider("clk48m", "spll", CCM_CSCR, 26, 3); in mx1_clocks_init()
73 clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, in mx1_clocks_init()
Dclk-imx27.c16 #define CCM_CSCR IO_ADDR_CCM(0x0) macro
102 clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, in mx27_clocks_init()
105 clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, in mx27_clocks_init()
109 clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); in mx27_clocks_init()
113 clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); in mx27_clocks_init()
116 clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); in mx27_clocks_init()
117 clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); in mx27_clocks_init()
125 clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); in mx27_clocks_init()
127 clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3); in mx27_clocks_init()
128 clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); in mx27_clocks_init()
[all …]
Dclk-imx21.c35 #define CCM_CSCR IO_ADDR_CCM(0x0) macro
78 clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, in mx21_clocks_init()
80 clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, in mx21_clocks_init()
84 clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 29, 3); in mx21_clocks_init()
85 clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4); in mx21_clocks_init()
86 clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1); in mx21_clocks_init()
108 clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 26, 3); in mx21_clocks_init()