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Searched refs:CHCTR (Results 1 – 11 of 11) sorted by relevance

/arch/mn10300/mm/
Dcache.inc16 # A0: Should hold CHCTR
17 # D0: Should have been read from CHCTR
77 # A0: Should hold CHCTR
78 # D0: Should have been read from CHCTR
Dcache-dbg-flush-by-reg.S35 movhu (CHCTR),d0
76 mov CHCTR,a0
Dcache-dbg-flush-by-tag.S36 movhu (CHCTR),d0
88 movhu (CHCTR),d1
Dcache-dbg-inv.S38 mov CHCTR,a0
Dcache-inv-by-reg.S60 mov CHCTR,a0
82 mov CHCTR,a0
Dcache-flush-by-tag.S52 movhu (CHCTR),d0
Dcache-flush-by-reg.S52 movhu (CHCTR),d0
112 movhu (CHCTR),d2
188 movhu (CHCTR),d0
245 movhu (CHCTR),d2
Dcache-inv-by-tag.S68 mov CHCTR,a0
90 mov CHCTR,a0
/arch/mn10300/kernel/
Dhead.S99 mov CHCTR,a0
395 mov (CHCTR),d0
Dsmp.c1018 : "a"(&CHCTR), in hotplug_cpu_disable_cache()
1032 : "a"(&CHCTR), in hotplug_cpu_enable_cache()
1045 : "a"(&CHCTR), in hotplug_cpu_invalidate_cache()
/arch/mn10300/include/asm/
Dcpu-regs.h172 #define CHCTR __SYSREG(0xc0000070, u16) /* cache control */ macro