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Searched refs:CPU (Results 1 – 25 of 152) sorted by relevance

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/arch/sparc/kernel/
Dcpu.c52 #define CPU(ver, _name) \ macro
66 CPU(0, "Fujitsu MB86900/1A or LSI L64831 SparcKIT-40"),
68 CPU(4, "Fujitsu MB86904"),
69 CPU(5, "Fujitsu TurboSparc MB86907"),
70 CPU(-1, NULL)
86 CPU(0, "LSI Logic Corporation - L64811"),
88 CPU(1, "Cypress/ROSS CY7C601"),
90 CPU(3, "Cypress/ROSS CY7C611"),
92 CPU(0xf, "ROSS HyperSparc RT620"),
93 CPU(0xe, "ROSS HyperSparc RT625 or RT626"),
[all …]
/arch/mips/bcm63xx/
DKconfig1 menu "CPU support"
5 bool "support 6328 CPU"
9 bool "support 6338 CPU"
16 bool "support 6345 CPU"
21 bool "support 6348 CPU"
25 bool "support 6358 CPU"
29 bool "support 6362 CPU"
33 bool "support 6368 CPU"
/arch/blackfin/mach-bf548/include/mach/
Dbf548.h85 # define CPU "BF542" macro
88 # define CPU "BF544" macro
91 # define CPU "BF547" macro
94 # define CPU "BF548" macro
97 # define CPU "BF549" macro
101 #ifndef CPU
/arch/mn10300/proc-mn2ws0050/include/proc/
Dsmp-regs.h31 #define CROSS_GxICR(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \ argument
32 ((X) >= 64 && (X) < 192) * 0xf00 + ((CPU) << CROSS_ICR_CPU_SHIFT), u16)
33 #define CROSS_GxICR_u8(X, CPU) __SYSREG(0xc4000000 + (X) * 4 + \ argument
34 (((X) >= 64) && ((X) < 192)) * 0xf00 + ((CPU) << CROSS_ICR_CPU_SHIFT), u8)
/arch/blackfin/mach-bf527/include/mach/
Dbf527.h209 #define CPU "BF527" macro
213 #define CPU "BF526" macro
217 #define CPU "BF525" macro
221 #define CPU "BF524" macro
225 #define CPU "BF523" macro
229 #define CPU "BF522" macro
233 #ifndef CPU
/arch/blackfin/mach-bf537/include/mach/
Dbf537.h92 #define CPU "BF537" macro
96 #define CPU "BF536" macro
100 #define CPU "BF534" macro
104 #ifndef CPU
/arch/blackfin/mach-bf518/include/mach/
Dbf518.h194 #define CPU "BF518" macro
198 #define CPU "BF516" macro
202 #define CPU "BF514" macro
206 #define CPU "BF512" macro
210 #ifndef CPU
/arch/blackfin/mach-bf533/include/mach/
Dbf533.h122 #define CPU "BF533" macro
126 #define CPU "BF532" macro
130 #define CPU "BF531" macro
134 #ifndef CPU
/arch/blackfin/mach-bf538/include/mach/
Dbf538.h91 #define CPU "BF538" macro
95 #define CPU "BF539" macro
99 #ifndef CPU
/arch/arm/common/
Dmcpm_head.S58 mla r4, r3, r10, r9 @ r4 = canonical CPU index
83 @ Signal that this CPU is coming UP:
90 @ state, because there is at least one active CPU (this CPU).
118 @ Any CPU trying to take the cluster into CLUSTER_GOING_DOWN from this
171 @ If a platform-specific CPU setup hook is needed, it is
175 mov r0, #0 @ first (CPU) affinity level
179 @ Mark the CPU as up:
187 ldr r5, [r6, r4, lsl #2] @ r5 = CPU entry vector
/arch/arm/mach-tegra/
Dsleep-tegra30.S53 moveq pc, lr @ Must never be called for CPU 0
57 add r1, r1, r12 @ virtual CSR address for this CPU
59 add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU
92 wfe @ CPU should be power gated here
DKconfig42 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
59 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
72 ARM CortexA15MP CPU
/arch/h8300/kernel/
Dsetup.c41 #define CPU "H8/300H" macro
46 #define CPU "H8S" macro
131 printk(KERN_INFO "\r\n\nuClinux " CPU "\n"); in setup_arch()
205 cpu = CPU; in show_cpuinfo()
/arch/blackfin/mach-bf609/include/mach/
Dbf609.h85 # define CPU "BF609" macro
89 #ifndef CPU
/arch/h8300/
DKconfig.cpu10 H8/300H CPU Generic Hardware Support
42 H8S CPU Generic Hardware Support
63 prompt "CPU Selection"
88 int "CPU Clock Frequency (/1KHz)"
91 CPU Clock Frequency divide to 1000
/arch/mips/jazz/
DKconfig7 This is a machine with a R4400 133/150 MHz CPU. To compile a Linux
19 This is a machine with a R4000 100 MHz CPU. To compile a Linux
30 This is a machine with a R4000 100 MHz CPU. To compile a Linux
/arch/m68k/
DKconfig.cpu4 prompt "CPU family support"
21 bool "Classic M68K CPU family support"
24 bool "Coldfire CPU family support"
44 The Freescale (was Motorola) 68000 CPU is the first generation of
45 the well known M68K family of processors. The CPU core as well as
46 being available as a stand alone CPU was also used in many
55 The Freescale (was then Motorola) CPU32 is a CPU core that is
325 This gives you access to some advanced options for the CPU. The
420 bool "Enable setting the CPU clock frequency"
424 On some CPU's you do not need to know what the core CPU clock
[all …]
/arch/x86/
DKconfig.cpu1 # Put here option for CPU selection and depending optimization
11 This is the processor type of your CPU. This information is
13 that can run on all supported x86 CPU types (albeit not
193 stores for this CPU, which can increase performance of some
221 treat this chip as a generic 586. Whilst the CPU is 686 class,
226 incarnations of the CPU.
233 of SSE and tells gcc to treat the CPU as a 686.
241 shift and tells gcc to treat the CPU as a 686.
259 53xx) CPUs. You can distinguish newer from older Xeons by the CPU
276 Generic x86-64 CPU.
[all …]
/arch/arm/kernel/
Dhyp-stub.S58 cmp \mode, \reg1 @ matches primary CPU boot mode?
85 @ Call this from the primary CPU
114 movne pc, lr @ give up if the CPU is not in HYP mode
/arch/frv/
DKconfig157 prompt "CPU Caching mode"
178 Note that not all CPUs support Write-Behind caching. If the CPU on
196 menu "CPU core support"
210 This enables support for the FR405 CPU
216 This enables support for the FR451 CPU
224 optimise for the FR451 CPU
231 This enables support for the FR555 CPU
239 optimise for the FR555 CPU
253 bool "MB93091 CPU board with or without motherboard"
268 Select this option if the MB93091 CPU board is going to be used with
[all …]
/arch/mn10300/kernel/
Dhead.S41 # If this is a secondary CPU (AP), then deal with that elsewhere
52 # Set up the Boot IPI for each secondary CPU
255 # mark the primary CPU in cpu_boot_map
260 # signal each secondary CPU to begin booting
261 mov 0x1,d2 # CPU ID
265 # send SMP_BOOT_IPI to secondary CPU
396 btst CHCTR_DCBUSY,d0 # wait till not busy (use CPU loop buffer)
/arch/sh/
DKconfig317 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
323 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
330 if you have a 100 Mhz SH-3 HD6417708R CPU.
336 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
343 Select SH7710 if you have a SH3-DSP SH7710 CPU.
350 Select SH7712 if you have a SH3-DSP SH7712 CPU.
362 Select SH7720 if you have a SH3-DSP SH7720 CPU.
372 Select SH7721 if you have a SH3-DSP SH7721 CPU.
380 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
401 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
[all …]
/arch/mn10300/boot/compressed/
Dhead.S28 # Must save primary CPU's D0-D2 registers as they hold boot parameters
/arch/blackfin/mach-bf561/include/mach/
Dbf561.h192 #define CPU "BF561" macro
196 #ifndef CPU
/arch/arm/mach-sa1100/
Dsleep.S50 @ Adjust memory timing before lowering CPU clock
53 @ delay 90us and set CPU PLL to lowest speed
137 @ about 7 ns out of the entire time that the CPU is running!

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