1 /* 2 * This file contains the hardware definitions of the Cirrus Logic 3 * ARM7 CLPS711X internal registers. 4 * 5 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 #ifndef __MACH_CLPS711X_H 22 #define __MACH_CLPS711X_H 23 24 #define CLPS711X_PHYS_BASE (0x80000000) 25 26 #define PADR (0x0000) 27 #define PBDR (0x0001) 28 #define PCDR (0x0002) 29 #define PDDR (0x0003) 30 #define PADDR (0x0040) 31 #define PBDDR (0x0041) 32 #define PCDDR (0x0042) 33 #define PDDDR (0x0043) 34 #define PEDR (0x0083) 35 #define PEDDR (0x00c3) 36 #define SYSCON1 (0x0100) 37 #define SYSFLG1 (0x0140) 38 #define MEMCFG1 (0x0180) 39 #define MEMCFG2 (0x01c0) 40 #define DRFPR (0x0200) 41 #define INTSR1 (0x0240) 42 #define INTMR1 (0x0280) 43 #define LCDCON (0x02c0) 44 #define TC1D (0x0300) 45 #define TC2D (0x0340) 46 #define RTCDR (0x0380) 47 #define RTCMR (0x03c0) 48 #define PMPCON (0x0400) 49 #define CODR (0x0440) 50 #define UARTDR1 (0x0480) 51 #define UBRLCR1 (0x04c0) 52 #define SYNCIO (0x0500) 53 #define PALLSW (0x0540) 54 #define PALMSW (0x0580) 55 #define STFCLR (0x05c0) 56 #define BLEOI (0x0600) 57 #define MCEOI (0x0640) 58 #define TEOI (0x0680) 59 #define TC1EOI (0x06c0) 60 #define TC2EOI (0x0700) 61 #define RTCEOI (0x0740) 62 #define UMSEOI (0x0780) 63 #define COEOI (0x07c0) 64 #define HALT (0x0800) 65 #define STDBY (0x0840) 66 67 #define FBADDR (0x1000) 68 #define SYSCON2 (0x1100) 69 #define SYSFLG2 (0x1140) 70 #define INTSR2 (0x1240) 71 #define INTMR2 (0x1280) 72 #define UARTDR2 (0x1480) 73 #define UBRLCR2 (0x14c0) 74 #define SS2DR (0x1500) 75 #define SRXEOF (0x1600) 76 #define SS2POP (0x16c0) 77 #define KBDEOI (0x1700) 78 79 #define DAIR (0x2000) 80 #define DAIDR0 (0x2040) 81 #define DAIDR1 (0x2080) 82 #define DAIDR2 (0x20c0) 83 #define DAISR (0x2100) 84 #define SYSCON3 (0x2200) 85 #define INTSR3 (0x2240) 86 #define INTMR3 (0x2280) 87 #define LEDFLSH (0x22c0) 88 #define SDCONF (0x2300) 89 #define SDRFPR (0x2340) 90 #define UNIQID (0x2440) 91 #define DAI64FS (0x2600) 92 #define PLLW (0x2610) 93 #define PLLR (0xa5a8) 94 #define RANDID0 (0x2700) 95 #define RANDID1 (0x2704) 96 #define RANDID2 (0x2708) 97 #define RANDID3 (0x270c) 98 99 /* common bits: SYSCON1 / SYSCON2 */ 100 #define SYSCON_UARTEN (1 << 8) 101 102 #define SYSCON1_KBDSCAN(x) ((x) & 15) 103 #define SYSCON1_KBDSCANMASK (15) 104 #define SYSCON1_TC1M (1 << 4) 105 #define SYSCON1_TC1S (1 << 5) 106 #define SYSCON1_TC2M (1 << 6) 107 #define SYSCON1_TC2S (1 << 7) 108 #define SYSCON1_UART1EN SYSCON_UARTEN 109 #define SYSCON1_BZTOG (1 << 9) 110 #define SYSCON1_BZMOD (1 << 10) 111 #define SYSCON1_DBGEN (1 << 11) 112 #define SYSCON1_LCDEN (1 << 12) 113 #define SYSCON1_CDENTX (1 << 13) 114 #define SYSCON1_CDENRX (1 << 14) 115 #define SYSCON1_SIREN (1 << 15) 116 #define SYSCON1_ADCKSEL(x) (((x) & 3) << 16) 117 #define SYSCON1_ADCKSEL_MASK (3 << 16) 118 #define SYSCON1_EXCKEN (1 << 18) 119 #define SYSCON1_WAKEDIS (1 << 19) 120 #define SYSCON1_IRTXM (1 << 20) 121 122 /* common bits: SYSFLG1 / SYSFLG2 */ 123 #define SYSFLG_UBUSY (1 << 11) 124 #define SYSFLG_URXFE (1 << 22) 125 #define SYSFLG_UTXFF (1 << 23) 126 127 #define SYSFLG1_MCDR (1 << 0) 128 #define SYSFLG1_DCDET (1 << 1) 129 #define SYSFLG1_WUDR (1 << 2) 130 #define SYSFLG1_WUON (1 << 3) 131 #define SYSFLG1_CTS (1 << 8) 132 #define SYSFLG1_DSR (1 << 9) 133 #define SYSFLG1_DCD (1 << 10) 134 #define SYSFLG1_UBUSY SYSFLG_UBUSY 135 #define SYSFLG1_NBFLG (1 << 12) 136 #define SYSFLG1_RSTFLG (1 << 13) 137 #define SYSFLG1_PFFLG (1 << 14) 138 #define SYSFLG1_CLDFLG (1 << 15) 139 #define SYSFLG1_URXFE SYSFLG_URXFE 140 #define SYSFLG1_UTXFF SYSFLG_UTXFF 141 #define SYSFLG1_CRXFE (1 << 24) 142 #define SYSFLG1_CTXFF (1 << 25) 143 #define SYSFLG1_SSIBUSY (1 << 26) 144 #define SYSFLG1_ID (1 << 29) 145 #define SYSFLG1_VERID(x) (((x) >> 30) & 3) 146 #define SYSFLG1_VERID_MASK (3 << 30) 147 148 #define SYSFLG2_SSRXOF (1 << 0) 149 #define SYSFLG2_RESVAL (1 << 1) 150 #define SYSFLG2_RESFRM (1 << 2) 151 #define SYSFLG2_SS2RXFE (1 << 3) 152 #define SYSFLG2_SS2TXFF (1 << 4) 153 #define SYSFLG2_SS2TXUF (1 << 5) 154 #define SYSFLG2_CKMODE (1 << 6) 155 #define SYSFLG2_UBUSY SYSFLG_UBUSY 156 #define SYSFLG2_URXFE SYSFLG_URXFE 157 #define SYSFLG2_UTXFF SYSFLG_UTXFF 158 159 #define LCDCON_GSEN (1 << 30) 160 #define LCDCON_GSMD (1 << 31) 161 162 #define SYSCON2_SERSEL (1 << 0) 163 #define SYSCON2_KBD6 (1 << 1) 164 #define SYSCON2_DRAMZ (1 << 2) 165 #define SYSCON2_KBWEN (1 << 3) 166 #define SYSCON2_SS2TXEN (1 << 4) 167 #define SYSCON2_PCCARD1 (1 << 5) 168 #define SYSCON2_PCCARD2 (1 << 6) 169 #define SYSCON2_SS2RXEN (1 << 7) 170 #define SYSCON2_UART2EN SYSCON_UARTEN 171 #define SYSCON2_SS2MAEN (1 << 9) 172 #define SYSCON2_OSTB (1 << 12) 173 #define SYSCON2_CLKENSL (1 << 13) 174 #define SYSCON2_BUZFREQ (1 << 14) 175 176 /* common bits: UARTDR1 / UARTDR2 */ 177 #define UARTDR_FRMERR (1 << 8) 178 #define UARTDR_PARERR (1 << 9) 179 #define UARTDR_OVERR (1 << 10) 180 181 /* common bits: UBRLCR1 / UBRLCR2 */ 182 #define UBRLCR_BAUD_MASK ((1 << 12) - 1) 183 #define UBRLCR_BREAK (1 << 12) 184 #define UBRLCR_PRTEN (1 << 13) 185 #define UBRLCR_EVENPRT (1 << 14) 186 #define UBRLCR_XSTOP (1 << 15) 187 #define UBRLCR_FIFOEN (1 << 16) 188 #define UBRLCR_WRDLEN5 (0 << 17) 189 #define UBRLCR_WRDLEN6 (1 << 17) 190 #define UBRLCR_WRDLEN7 (2 << 17) 191 #define UBRLCR_WRDLEN8 (3 << 17) 192 #define UBRLCR_WRDLEN_MASK (3 << 17) 193 194 #define SYNCIO_FRMLEN(x) (((x) & 0x1f) << 8) 195 #define SYNCIO_SMCKEN (1 << 13) 196 #define SYNCIO_TXFRMEN (1 << 14) 197 198 #define DAIR_RESERVED (0x0404) 199 #define DAIR_DAIEN (1 << 16) 200 #define DAIR_ECS (1 << 17) 201 #define DAIR_LCTM (1 << 19) 202 #define DAIR_LCRM (1 << 20) 203 #define DAIR_RCTM (1 << 21) 204 #define DAIR_RCRM (1 << 22) 205 #define DAIR_LBM (1 << 23) 206 207 #define DAIDR2_FIFOEN (1 << 15) 208 #define DAIDR2_FIFOLEFT (0x0d << 16) 209 #define DAIDR2_FIFORIGHT (0x11 << 16) 210 211 #define DAISR_RCTS (1 << 0) 212 #define DAISR_RCRS (1 << 1) 213 #define DAISR_LCTS (1 << 2) 214 #define DAISR_LCRS (1 << 3) 215 #define DAISR_RCTU (1 << 4) 216 #define DAISR_RCRO (1 << 5) 217 #define DAISR_LCTU (1 << 6) 218 #define DAISR_LCRO (1 << 7) 219 #define DAISR_RCNF (1 << 8) 220 #define DAISR_RCNE (1 << 9) 221 #define DAISR_LCNF (1 << 10) 222 #define DAISR_LCNE (1 << 11) 223 #define DAISR_FIFO (1 << 12) 224 225 #define DAI64FS_I2SF64 (1 << 0) 226 #define DAI64FS_AUDIOCLKEN (1 << 1) 227 #define DAI64FS_AUDIOCLKSRC (1 << 2) 228 #define DAI64FS_MCLK256EN (1 << 3) 229 #define DAI64FS_LOOPBACK (1 << 5) 230 231 #define SYSCON3_ADCCON (1 << 0) 232 #define SYSCON3_CLKCTL0 (1 << 1) 233 #define SYSCON3_CLKCTL1 (1 << 2) 234 #define SYSCON3_DAISEL (1 << 3) 235 #define SYSCON3_ADCCKNSEN (1 << 4) 236 #define SYSCON3_VERSN(x) (((x) >> 5) & 7) 237 #define SYSCON3_VERSN_MASK (7 << 5) 238 #define SYSCON3_FASTWAKE (1 << 8) 239 #define SYSCON3_DAIEN (1 << 9) 240 #define SYSCON3_128FS SYSCON3_DAIEN 241 #define SYSCON3_ENPD67 (1 << 10) 242 243 #define SDCONF_ACTIVE (1 << 10) 244 #define SDCONF_CLKCTL (1 << 9) 245 #define SDCONF_WIDTH_4 (0 << 7) 246 #define SDCONF_WIDTH_8 (1 << 7) 247 #define SDCONF_WIDTH_16 (2 << 7) 248 #define SDCONF_WIDTH_32 (3 << 7) 249 #define SDCONF_SIZE_16 (0 << 5) 250 #define SDCONF_SIZE_64 (1 << 5) 251 #define SDCONF_SIZE_128 (2 << 5) 252 #define SDCONF_SIZE_256 (3 << 5) 253 #define SDCONF_CASLAT_2 (2) 254 #define SDCONF_CASLAT_3 (3) 255 256 #define MEMCFG_BUS_WIDTH_32 (1) 257 #define MEMCFG_BUS_WIDTH_16 (0) 258 #define MEMCFG_BUS_WIDTH_8 (3) 259 260 #define MEMCFG_SQAEN (1 << 6) 261 #define MEMCFG_CLKENB (1 << 7) 262 263 #define MEMCFG_WAITSTATE_8_3 (0 << 2) 264 #define MEMCFG_WAITSTATE_7_3 (1 << 2) 265 #define MEMCFG_WAITSTATE_6_3 (2 << 2) 266 #define MEMCFG_WAITSTATE_5_3 (3 << 2) 267 #define MEMCFG_WAITSTATE_4_2 (4 << 2) 268 #define MEMCFG_WAITSTATE_3_2 (5 << 2) 269 #define MEMCFG_WAITSTATE_2_2 (6 << 2) 270 #define MEMCFG_WAITSTATE_1_2 (7 << 2) 271 #define MEMCFG_WAITSTATE_8_1 (8 << 2) 272 #define MEMCFG_WAITSTATE_7_1 (9 << 2) 273 #define MEMCFG_WAITSTATE_6_1 (10 << 2) 274 #define MEMCFG_WAITSTATE_5_1 (11 << 2) 275 #define MEMCFG_WAITSTATE_4_0 (12 << 2) 276 #define MEMCFG_WAITSTATE_3_0 (13 << 2) 277 #define MEMCFG_WAITSTATE_2_0 (14 << 2) 278 #define MEMCFG_WAITSTATE_1_0 (15 << 2) 279 280 /* INTSR1 Interrupts */ 281 #define IRQ_CSINT (4) 282 #define IRQ_EINT1 (5) 283 #define IRQ_EINT2 (6) 284 #define IRQ_EINT3 (7) 285 #define IRQ_TC1OI (8) 286 #define IRQ_TC2OI (9) 287 #define IRQ_RTCMI (10) 288 #define IRQ_TINT (11) 289 #define IRQ_UTXINT1 (12) 290 #define IRQ_URXINT1 (13) 291 #define IRQ_UMSINT (14) 292 #define IRQ_SSEOTI (15) 293 294 /* INTSR2 Interrupts */ 295 #define IRQ_KBDINT (16 + 0) 296 #define IRQ_SS2RX (16 + 1) 297 #define IRQ_SS2TX (16 + 2) 298 #define IRQ_UTXINT2 (16 + 12) 299 #define IRQ_URXINT2 (16 + 13) 300 301 /* INTSR3 Interrupts */ 302 #define IRQ_DAIINT (32 + 0) 303 304 #endif /* __MACH_CLPS711X_H */ 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