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Searched refs:DEFINE_CLK (Results 1 – 21 of 21) sorted by relevance

/arch/m68k/platform/coldfire/
Dm5441x.c19 DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
20 DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
21 DEFINE_CLK(0, "mcfcan.1", 9, MCF_CLK);
22 DEFINE_CLK(0, "mcfi2c.1", 14, MCF_CLK);
23 DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK);
24 DEFINE_CLK(0, "edma", 17, MCF_CLK);
25 DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
26 DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
27 DEFINE_CLK(0, "intc.2", 20, MCF_CLK);
28 DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
[all …]
Dm520x.c26 DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
27 DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
28 DEFINE_CLK(0, "edma", 17, MCF_CLK);
29 DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
30 DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
31 DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
32 DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
33 DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
34 DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
35 DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
[all …]
Dm523x.c26 DEFINE_CLK(pll, "pll.0", MCF_CLK);
27 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
28 DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
29 DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
30 DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
31 DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
32 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
33 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
34 DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
35 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
Dm53xx.c34 DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
35 DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
36 DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
37 DEFINE_CLK(0, "edma", 17, MCF_CLK);
38 DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
39 DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
40 DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
41 DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
42 DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
43 DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
[all …]
Dm528x.c28 DEFINE_CLK(pll, "pll.0", MCF_CLK);
29 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
30 DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
31 DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
32 DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
33 DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
34 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
35 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
36 DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
37 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
Dm527x.c27 DEFINE_CLK(pll, "pll.0", MCF_CLK);
28 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
29 DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
30 DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
31 DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
32 DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
33 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
34 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
35 DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
36 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
[all …]
Dm5272.c34 DEFINE_CLK(pll, "pll.0", MCF_CLK);
35 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
36 DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
37 DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
38 DEFINE_CLK(mcftmr2, "mcftmr.2", MCF_BUSCLK);
39 DEFINE_CLK(mcftmr3, "mcftmr.3", MCF_BUSCLK);
40 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
41 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
42 DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
Dm5407.c23 DEFINE_CLK(pll, "pll.0", MCF_CLK);
24 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
25 DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26 DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
Dm5206.c23 DEFINE_CLK(pll, "pll.0", MCF_CLK);
24 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
25 DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26 DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
Dm5307.c32 DEFINE_CLK(pll, "pll.0", MCF_CLK);
33 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
34 DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
35 DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
36 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
37 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
Dm54xx.c33 DEFINE_CLK(pll, "pll.0", MCF_CLK);
34 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
35 DEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK);
36 DEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK);
37 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
38 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
39 DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
40 DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK);
Dm525x.c23 DEFINE_CLK(pll, "pll.0", MCF_CLK);
24 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
25 DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26 DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
Dm5249.c23 DEFINE_CLK(pll, "pll.0", MCF_CLK);
24 DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
25 DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
26 DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
27 DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
28 DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
/arch/arm/mach-w90x900/
Dcpu.c55 static DEFINE_CLK(lcd, 0);
56 static DEFINE_CLK(audio, 1);
57 static DEFINE_CLK(fmi, 4);
60 static DEFINE_CLK(dmac, 5);
61 static DEFINE_CLK(atapi, 6);
62 static DEFINE_CLK(emc, 7);
64 static DEFINE_CLK(usbd, 8);
65 static DEFINE_CLK(usbh, 9);
66 static DEFINE_CLK(g2d, 10);
67 static DEFINE_CLK(pwm, 18);
[all …]
Dclock.h24 #define DEFINE_CLK(_name, _ctrlbit) \ macro
/arch/m68k/include/asm/
Dmcfclk.h32 #define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \ macro
43 #define DEFINE_CLK(clk_ref, clk_name, clk_rate) \ macro
/arch/arm/mach-sa1100/
Dclock.c29 #define DEFINE_CLK(_name, _ops) \ macro
88 static DEFINE_CLK(gpio27, &clk_gpio27_ops);
/arch/arm/mach-pxa/
Dpxa25x.c187 static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
188 static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
189 static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);
Dclock.h38 #define DEFINE_CLK(_name, _ops, _rate, _delay) \ macro
Dpxa27x.c210 static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
Dpxa3xx.c69 static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);