Searched refs:EBIU_AMBCTL0 (Results 1 – 17 of 17) sorted by relevance
255 PM_SYS_PUSH(8, EBIU_AMBCTL0)285 PM_SYS_POP(8, EBIU_AMBCTL0)
171 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ macro
468 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)469 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
208 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ macro
373 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)374 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
209 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ macro
356 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)357 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
283 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ macro
480 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)481 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
185 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ macro
336 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)337 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
178 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ macro
470 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)471 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
154 #define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register… macro
215 #define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)216 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
1181 These are the low 16 bits of the EBIU_AMBCTL0 MMR which are1189 These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
880 D32(EBIU_AMBCTL0); in bfin_debug_mmrs_init()