1 /* 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef _ASM_ARC_ARCREGS_H 10 #define _ASM_ARC_ARCREGS_H 11 12 #ifdef __KERNEL__ 13 14 /* Build Configuration Registers */ 15 #define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */ 16 #define ARC_REG_CRC_BCR 0x62 17 #define ARC_REG_DVFB_BCR 0x64 18 #define ARC_REG_EXTARITH_BCR 0x65 19 #define ARC_REG_VECBASE_BCR 0x68 20 #define ARC_REG_PERIBASE_BCR 0x69 21 #define ARC_REG_FP_BCR 0x6B /* Single-Precision FPU */ 22 #define ARC_REG_DPFP_BCR 0x6C /* Dbl Precision FPU */ 23 #define ARC_REG_MMU_BCR 0x6f 24 #define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */ 25 #define ARC_REG_TIMERS_BCR 0x75 26 #define ARC_REG_ICCM_BCR 0x78 27 #define ARC_REG_XY_MEM_BCR 0x79 28 #define ARC_REG_MAC_BCR 0x7a 29 #define ARC_REG_MUL_BCR 0x7b 30 #define ARC_REG_SWAP_BCR 0x7c 31 #define ARC_REG_NORM_BCR 0x7d 32 #define ARC_REG_MIXMAX_BCR 0x7e 33 #define ARC_REG_BARREL_BCR 0x7f 34 #define ARC_REG_D_UNCACH_BCR 0x6A 35 36 /* status32 Bits Positions */ 37 #define STATUS_H_BIT 0 /* CPU Halted */ 38 #define STATUS_E1_BIT 1 /* Int 1 enable */ 39 #define STATUS_E2_BIT 2 /* Int 2 enable */ 40 #define STATUS_A1_BIT 3 /* Int 1 active */ 41 #define STATUS_A2_BIT 4 /* Int 2 active */ 42 #define STATUS_AE_BIT 5 /* Exception active */ 43 #define STATUS_DE_BIT 6 /* PC is in delay slot */ 44 #define STATUS_U_BIT 7 /* User/Kernel mode */ 45 #define STATUS_L_BIT 12 /* Loop inhibit */ 46 47 /* These masks correspond to the status word(STATUS_32) bits */ 48 #define STATUS_H_MASK (1<<STATUS_H_BIT) 49 #define STATUS_E1_MASK (1<<STATUS_E1_BIT) 50 #define STATUS_E2_MASK (1<<STATUS_E2_BIT) 51 #define STATUS_A1_MASK (1<<STATUS_A1_BIT) 52 #define STATUS_A2_MASK (1<<STATUS_A2_BIT) 53 #define STATUS_AE_MASK (1<<STATUS_AE_BIT) 54 #define STATUS_DE_MASK (1<<STATUS_DE_BIT) 55 #define STATUS_U_MASK (1<<STATUS_U_BIT) 56 #define STATUS_L_MASK (1<<STATUS_L_BIT) 57 58 /* 59 * ECR: Exception Cause Reg bits-n-pieces 60 * [23:16] = Exception Vector 61 * [15: 8] = Exception Cause Code 62 * [ 7: 0] = Exception Parameters (for certain types only) 63 */ 64 #define ECR_VEC_MASK 0xff0000 65 #define ECR_CODE_MASK 0x00ff00 66 #define ECR_PARAM_MASK 0x0000ff 67 68 /* Exception Cause Vector Values */ 69 #define ECR_V_INSN_ERR 0x02 70 #define ECR_V_MACH_CHK 0x20 71 #define ECR_V_ITLB_MISS 0x21 72 #define ECR_V_DTLB_MISS 0x22 73 #define ECR_V_PROTV 0x23 74 75 /* Protection Violation Exception Cause Code Values */ 76 #define ECR_C_PROTV_INST_FETCH 0x00 77 #define ECR_C_PROTV_LOAD 0x01 78 #define ECR_C_PROTV_STORE 0x02 79 #define ECR_C_PROTV_XCHG 0x03 80 #define ECR_C_PROTV_MISALIG_DATA 0x04 81 82 /* DTLB Miss Exception Cause Code Values */ 83 #define ECR_C_BIT_DTLB_LD_MISS 8 84 #define ECR_C_BIT_DTLB_ST_MISS 9 85 86 87 /* Auxiliary registers */ 88 #define AUX_IDENTITY 4 89 #define AUX_INTR_VEC_BASE 0x25 90 #define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */ 91 #define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */ 92 #define AUX_IRQ_LV12 0x43 /* interrupt level register */ 93 94 #define AUX_IENABLE 0x40c 95 #define AUX_ITRIGGER 0x40d 96 #define AUX_IPULSE 0x415 97 98 /* Timer related Aux registers */ 99 #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ 100 #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */ 101 #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */ 102 #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */ 103 #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */ 104 #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ 105 106 #define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */ 107 #define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ 108 109 /* MMU Management regs */ 110 #define ARC_REG_TLBPD0 0x405 111 #define ARC_REG_TLBPD1 0x406 112 #define ARC_REG_TLBINDEX 0x407 113 #define ARC_REG_TLBCOMMAND 0x408 114 #define ARC_REG_PID 0x409 115 #define ARC_REG_SCRATCH_DATA0 0x418 116 117 /* Bits in MMU PID register */ 118 #define MMU_ENABLE (1 << 31) /* Enable MMU for process */ 119 120 /* Error code if probe fails */ 121 #define TLB_LKUP_ERR 0x80000000 122 123 /* TLB Commands */ 124 #define TLBWrite 0x1 125 #define TLBRead 0x2 126 #define TLBGetIndex 0x3 127 #define TLBProbe 0x4 128 129 #if (CONFIG_ARC_MMU_VER >= 2) 130 #define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */ 131 #define TLBIVUTLB 0x6 /* explicitly inv uTLBs */ 132 #else 133 #undef TLBWriteNI /* These cmds don't exist on older MMU */ 134 #undef TLBIVUTLB 135 #endif 136 137 /* Instruction cache related Auxiliary registers */ 138 #define ARC_REG_IC_BCR 0x77 /* Build Config reg */ 139 #define ARC_REG_IC_IVIC 0x10 140 #define ARC_REG_IC_CTRL 0x11 141 #define ARC_REG_IC_IVIL 0x19 142 #if (CONFIG_ARC_MMU_VER > 2) 143 #define ARC_REG_IC_PTAG 0x1E 144 #endif 145 146 /* Bit val in IC_CTRL */ 147 #define IC_CTRL_CACHE_DISABLE 0x1 148 149 /* Data cache related Auxiliary registers */ 150 #define ARC_REG_DC_BCR 0x72 151 #define ARC_REG_DC_IVDC 0x47 152 #define ARC_REG_DC_CTRL 0x48 153 #define ARC_REG_DC_IVDL 0x4A 154 #define ARC_REG_DC_FLSH 0x4B 155 #define ARC_REG_DC_FLDL 0x4C 156 #if (CONFIG_ARC_MMU_VER > 2) 157 #define ARC_REG_DC_PTAG 0x5C 158 #endif 159 160 /* Bit val in DC_CTRL */ 161 #define DC_CTRL_INV_MODE_FLUSH 0x40 162 #define DC_CTRL_FLUSH_STATUS 0x100 163 164 /* MMU Management regs */ 165 #define ARC_REG_PID 0x409 166 #define ARC_REG_SCRATCH_DATA0 0x418 167 168 /* Bits in MMU PID register */ 169 #define MMU_ENABLE (1 << 31) /* Enable MMU for process */ 170 171 /* 172 * Floating Pt Registers 173 * Status regs are read-only (build-time) so need not be saved/restored 174 */ 175 #define ARC_AUX_FP_STAT 0x300 176 #define ARC_AUX_DPFP_1L 0x301 177 #define ARC_AUX_DPFP_1H 0x302 178 #define ARC_AUX_DPFP_2L 0x303 179 #define ARC_AUX_DPFP_2H 0x304 180 #define ARC_AUX_DPFP_STAT 0x305 181 182 #ifndef __ASSEMBLY__ 183 184 /* 185 ****************************************************************** 186 * Inline ASM macros to read/write AUX Regs 187 * Essentially invocation of lr/sr insns from "C" 188 */ 189 190 #if 1 191 192 #define read_aux_reg(reg) __builtin_arc_lr(reg) 193 194 /* gcc builtin sr needs reg param to be long immediate */ 195 #define write_aux_reg(reg_immed, val) \ 196 __builtin_arc_sr((unsigned int)val, reg_immed) 197 198 #else 199 200 #define read_aux_reg(reg) \ 201 ({ \ 202 unsigned int __ret; \ 203 __asm__ __volatile__( \ 204 " lr %0, [%1]" \ 205 : "=r"(__ret) \ 206 : "i"(reg)); \ 207 __ret; \ 208 }) 209 210 /* 211 * Aux Reg address is specified as long immediate by caller 212 * e.g. 213 * write_aux_reg(0x69, some_val); 214 * This generates tightest code. 215 */ 216 #define write_aux_reg(reg_imm, val) \ 217 ({ \ 218 __asm__ __volatile__( \ 219 " sr %0, [%1] \n" \ 220 : \ 221 : "ir"(val), "i"(reg_imm)); \ 222 }) 223 224 /* 225 * Aux Reg address is specified in a variable 226 * * e.g. 227 * reg_num = 0x69 228 * write_aux_reg2(reg_num, some_val); 229 * This has to generate glue code to load the reg num from 230 * memory to a reg hence not recommended. 231 */ 232 #define write_aux_reg2(reg_in_var, val) \ 233 ({ \ 234 unsigned int tmp; \ 235 \ 236 __asm__ __volatile__( \ 237 " ld %0, [%2] \n\t" \ 238 " sr %1, [%0] \n\t" \ 239 : "=&r"(tmp) \ 240 : "r"(val), "memory"(®_in_var)); \ 241 }) 242 243 #endif 244 245 #define READ_BCR(reg, into) \ 246 { \ 247 unsigned int tmp; \ 248 tmp = read_aux_reg(reg); \ 249 if (sizeof(tmp) == sizeof(into)) { \ 250 into = *((typeof(into) *)&tmp); \ 251 } else { \ 252 extern void bogus_undefined(void); \ 253 bogus_undefined(); \ 254 } \ 255 } 256 257 #define WRITE_BCR(reg, into) \ 258 { \ 259 unsigned int tmp; \ 260 if (sizeof(tmp) == sizeof(into)) { \ 261 tmp = (*(unsigned int *)(into)); \ 262 write_aux_reg(reg, tmp); \ 263 } else { \ 264 extern void bogus_undefined(void); \ 265 bogus_undefined(); \ 266 } \ 267 } 268 269 /* Helpers */ 270 #define TO_KB(bytes) ((bytes) >> 10) 271 #define TO_MB(bytes) (TO_KB(bytes) >> 10) 272 #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10)) 273 #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10) 274 275 #ifdef CONFIG_ARC_FPU_SAVE_RESTORE 276 /* These DPFP regs need to be saved/restored across ctx-sw */ 277 struct arc_fpu { 278 struct { 279 unsigned int l, h; 280 } aux_dpfp[2]; 281 }; 282 #endif 283 284 /* 285 *************************************************************** 286 * Build Configuration Registers, with encoded hardware config 287 */ 288 struct bcr_identity { 289 #ifdef CONFIG_CPU_BIG_ENDIAN 290 unsigned int chip_id:16, cpu_id:8, family:8; 291 #else 292 unsigned int family:8, cpu_id:8, chip_id:16; 293 #endif 294 }; 295 296 struct bcr_mmu_1_2 { 297 #ifdef CONFIG_CPU_BIG_ENDIAN 298 unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8; 299 #else 300 unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8; 301 #endif 302 }; 303 304 struct bcr_mmu_3 { 305 #ifdef CONFIG_CPU_BIG_ENDIAN 306 unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4, 307 u_itlb:4, u_dtlb:4; 308 #else 309 unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4, 310 ways:4, ver:8; 311 #endif 312 }; 313 314 #define EXTN_SWAP_VALID 0x1 315 #define EXTN_NORM_VALID 0x2 316 #define EXTN_MINMAX_VALID 0x2 317 #define EXTN_BARREL_VALID 0x2 318 319 struct bcr_extn { 320 #ifdef CONFIG_CPU_BIG_ENDIAN 321 unsigned int pad:20, crc:1, ext_arith:2, mul:2, barrel:2, minmax:2, 322 norm:2, swap:1; 323 #else 324 unsigned int swap:1, norm:2, minmax:2, barrel:2, mul:2, ext_arith:2, 325 crc:1, pad:20; 326 #endif 327 }; 328 329 /* DSP Options Ref Manual */ 330 struct bcr_extn_mac_mul { 331 #ifdef CONFIG_CPU_BIG_ENDIAN 332 unsigned int pad:16, type:8, ver:8; 333 #else 334 unsigned int ver:8, type:8, pad:16; 335 #endif 336 }; 337 338 struct bcr_extn_xymem { 339 #ifdef CONFIG_CPU_BIG_ENDIAN 340 unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8; 341 #else 342 unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2; 343 #endif 344 }; 345 346 struct bcr_cache { 347 #ifdef CONFIG_CPU_BIG_ENDIAN 348 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; 349 #else 350 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; 351 #endif 352 }; 353 354 struct bcr_perip { 355 #ifdef CONFIG_CPU_BIG_ENDIAN 356 unsigned int start:8, pad2:8, sz:8, pad:8; 357 #else 358 unsigned int pad:8, sz:8, pad2:8, start:8; 359 #endif 360 }; 361 struct bcr_iccm { 362 #ifdef CONFIG_CPU_BIG_ENDIAN 363 unsigned int base:16, pad:5, sz:3, ver:8; 364 #else 365 unsigned int ver:8, sz:3, pad:5, base:16; 366 #endif 367 }; 368 369 /* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */ 370 struct bcr_dccm_base { 371 #ifdef CONFIG_CPU_BIG_ENDIAN 372 unsigned int addr:24, ver:8; 373 #else 374 unsigned int ver:8, addr:24; 375 #endif 376 }; 377 378 /* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */ 379 struct bcr_dccm { 380 #ifdef CONFIG_CPU_BIG_ENDIAN 381 unsigned int res:21, sz:3, ver:8; 382 #else 383 unsigned int ver:8, sz:3, res:21; 384 #endif 385 }; 386 387 /* Both SP and DP FPU BCRs have same format */ 388 struct bcr_fp { 389 #ifdef CONFIG_CPU_BIG_ENDIAN 390 unsigned int fast:1, ver:8; 391 #else 392 unsigned int ver:8, fast:1; 393 #endif 394 }; 395 396 /* 397 ******************************************************************* 398 * Generic structures to hold build configuration used at runtime 399 */ 400 401 struct cpuinfo_arc_mmu { 402 unsigned int ver, pg_sz, sets, ways, u_dtlb, u_itlb, num_tlb; 403 }; 404 405 struct cpuinfo_arc_cache { 406 unsigned int has_aliasing, sz, line_len, assoc, ver; 407 }; 408 409 struct cpuinfo_arc_ccm { 410 unsigned int base_addr, sz; 411 }; 412 413 struct cpuinfo_arc { 414 struct cpuinfo_arc_cache icache, dcache; 415 struct cpuinfo_arc_mmu mmu; 416 struct bcr_identity core; 417 unsigned int timers; 418 unsigned int vec_base; 419 unsigned int uncached_base; 420 struct cpuinfo_arc_ccm iccm, dccm; 421 struct bcr_extn extn; 422 struct bcr_extn_xymem extn_xymem; 423 struct bcr_extn_mac_mul extn_mac_mul; 424 struct bcr_fp fp, dpfp; 425 }; 426 427 extern struct cpuinfo_arc cpuinfo_arc700[]; 428 429 #endif /* __ASEMBLY__ */ 430 431 #endif /* __KERNEL__ */ 432 433 #endif /* _ASM_ARC_ARCREGS_H */ 434