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Searched refs:EXYNOS5_DISP1_SYS_PWR_REG (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/
Dpmu.c297 { EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
/arch/arm/mach-exynos/include/mach/
Dregs-pmu.h321 #define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414) macro