Searched refs:EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG (Results 1 – 2 of 2) sorted by relevance
274 { EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
298 #define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220) macro