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Searched refs:HI (Results 1 – 25 of 27) sorted by relevance

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/arch/metag/lib/
Dashrdi3.S23 LSL D0Ar6,D1Re0,D1Ar3 ! TMP= HI << -(COUNT - 32)
26 ASR D1Re0,D1Re0,D1Ar3 ! HI = HI >> COUNT
30 ASR D0Re0,D1Re0,D1Ar3 ! LO = HI >> N
31 ASR D1Re0,D1Re0,#31 ! HI = HI >> 31
Dashldi3.S21 LSL D1Re0,D1Re0,D1Ar3 ! HI = HI << COUNT
23 OR D1Re0,D1Re0,D0Ar6 ! HI = HI | TMP
30 LSL D1Re0,D0Re0,D0Ar4 ! HI = LO << N
Dlshrdi3.S23 LSL D0Ar6,D1Re0,D1Ar3 ! TMP= HI << -(COUNT - 32)
26 LSR D1Re0,D1Re0,D1Ar3 ! HI = HI >> COUNT
30 LSR D0Re0,D1Re0,D1Ar3 ! LO = HI >> N
31 MOV D1Re0,#0 ! HI = 0
Ddiv64.S81 TSTT D1Ar1,#HI(0x80000000)
88 TSTT D1Ar3,#HI(0x80000000)
96 TSTT D1.5,#HI(0x80000000)
/arch/blackfin/mach-bf609/
Ddpm.S12 P0.H = HI(PM_STACK);
19 P0.H = HI(DPM0_RESTORE4);
25 P0.H = HI(DPM0_CTL);
27 R3.H = HI(0x00000010);
47 P0.h = HI(SEC_SCI_BASE + SEC_CSID);
52 P1.h = HI(SEC_END);
83 P0.H = HI(PM_STACK);
95 P0.H = HI(DPM0_CTL);
97 R3.H = HI(0x00000008);
/arch/hexagon/kernel/
Dhead.S43 r24.H = #HI(swapper_pg_dir)
53 r1.h = #HI(PAGE_OFFSET);
80 r1.h = #HI(_end);
81 r2.h = #HI(stext);
109 R1.H = #HI(PAGE_OFFSET >> (22 - 2))
200 {r29.H = #HI(init_thread_union); r0.H = #HI(_THREAD_SIZE); }
209 { r0.H = #HI(__bss_start); r2.h = #HI(__bss_stop); }
217 r0.h = #HI(__phys_offset);
Dvm_entry.S74 R2.H = #HI(_THREAD_SIZE); } \
233 R1.H = #HI(CHandler); \
299 R26.H = #HI(do_work_pending);
378 R26.H = #HI(do_work_pending);
/arch/metag/tbx/
Dtbictxfpu.S47 MOVT D0Ar4, #HI(METAC_CORE_ID)
55 ORT D0Ar4, D0Ar4, #HI(TBICTX_CFGFPU_FX16_BIT)
70 ANDT D0Ar6, D0Ar6, #HI(TXMODE_FPURMODE_BITS)
71 ORT D0Ar6, D0Ar6, #HI(TXMODE_FPURMODEWRITE_BIT)
78 TSTT D0Ar4, #HI(TBICTX_CFGFPU_FX16_BIT) /* Perform test here for extended FPU registers
145 ANDT D1Re0, D1Re0, #HI(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS)
150 ANDMT D1Ar5, D1Ar5, #HI(~(TXDEFR_FPE_FE_BITS|TXDEFR_FPE_ICTRL_BITS))
157 ANDMT D1Ar5, D1Ar5, #HI(~TXMODE_FPURMODE_BITS)
158 ANDT D0Ar6, D0Ar6, #HI(TXMODE_FPURMODE_BITS|TXMODE_FPURMODEWRITE_BIT)
162 TSTT D0Ar4, #HI(TBICTX_CFGFPU_FX16_BIT) /* Perform test here for extended FPU registers
Dtbidefr.S50 ANDT D0.5, D0.5, #HI(0xFFFF0000)
52 ANDT D1Ar3, D1Ar3, #HI(0xFFFF0000)
57 ANDT D1Ar3, D1Ar3, #HI(TXSTAT_BUSERR_BIT | TXSTAT_FPE_BITS)
69 MOVT D1Re0, #HI(TXSTAT_FPE_BITS & ~TXSTAT_FPE_DENORMAL_BIT)
120 ANDT D1Ar3, D1Ar3, #HI(TXSTAT_BUSERR_BIT | TXSTAT_FPE_BITS)
139 MOVT D1Re0, #HI(TXSTAT_FPE_BITS & ~TXSTAT_FPE_DENORMAL_BIT)
Dtbipcx.S65 MOVT D0Re0,#HI(LINCORE_BASE)
72 MOVT D0FrT,#HI(___TBIBoingRTI+4)
85 MOVT D1Ar5,#HI(___TBIBoingExit) /* Go here to return */
108 MOVT A0.2, #HI($Lpcx_target)
149 TSTT D1Ar1,#HI(TXDIVTIME_RPDIRTY_BIT)/* NZ = RPDIRTY */
158 TSTT D0Re0,#HI(TXSTATUS_FPACTIVE_BIT)
180 TSTT D0Re0,#HI(TXSTATUS_FPACTIVE_BIT)
183 ANDT D1Ar3,D1Ar3,#HI(TXDIVTIME_IRQENC_BITS)
189 MOVT A1LbP,#HI(___pTBIs)
263 ANDST D1Ar3,D1Ar3,#HI(TXDIVTIME_RPMASK_BITS)/* !Z if RPDIRTY */
[all …]
Dtbitimer.S66 MOVT D0FrT,#HI(___TBITimeCore) /* Get timer core reg values */
91 MOVT D0FrT,#HI(___TBITimeCore) /* Get timer core reg values */
115 MOVT D0FrT,#HI(___TBITimeCore) /* Get timer core reg values */
147 MOVT D0FrT,#HI(___TBITimeCore) /* Get timer core reg values */
177 TSTT D1Ar1,#HI(TBID_ISTAT_BIT) /* Interrupt level timer? */
179 MOVT A1LbP,#HI(___TBITimes)
Dtbiroot.S46 TSTT D1Ar1,#HI(TBID_ISTAT_BIT) /* Bgnd or Int level? */
47 MOVT A1LbP,#HI(___pTBIs)
71 ANDT D1Re0,D1Re0,#HI(TXSTATUS_ISTAT_BIT) /* +TXSTATUS_PSTAT_BIT) */
Dtbisoft.S82 MOVT D1Re0,#HI($LSwitchExit) /* ASync resume point here */
155 MOVT A1LbP,#HI(__exit)
181 MOVT A1LbP,#HI(__exit)
193 MOVT D1RtP,#HI(___TBIStart) /* Start up code for new stack */
202 MOVT D1Ar1,#HI($LSwitchExit) /* Async restore code */
229 MOVT A1LbP,#HI(__exit)
Dtbicore.S39 MOVT A1LbP,#HI(___pTBISegs)
57 MOVT A1LbP,#HI(___pTBISegs)
115 MOVT A0.3,#HI(LINSYSEVENT_WR_ATOMIC_LOCK)
/arch/metag/kernel/
Dhead.S18 MOVT D0Re0,#HI(___pTBIs)
21 MOVT D0Re0,#HI(___pTBISegs)
34 MOVT A0StP,#HI(_init_thread_union)
37 MOVT D1RtP,#HI(_metag_start_kernel)
55 MOVT D0Re0,#HI(LINSYSEVENT_WR_ATOMIC_UNLOCK)
59 MOVT A0StP,#HI(_secondary_data_stack)
Dftrace_stub.S19 MOVT D0Re0,#HI(_function_trace_stop)
33 MOVT D1RtP,#HI(_ftrace_stub)
45 MOVT D0Re0,#HI(_function_trace_stop)
55 MOVT D0Re0,#HI(_ftrace_trace_function)
58 MOVT D1Re0,#HI(_ftrace_stub)
Duser_gateway.S39 MOVT D1Ar1,#HI(USER_GATEWAY_PAGE + USER_GATEWAY_TLS)
75 ANDT D0Re0,D0Re0,#HI(0x3f000000)
76 CMPT D0Re0,#HI(0x02000000)
/arch/blackfin/include/asm/
Dtrace.h63 preg.H = HI(TBUFCTL); \
69 preg.H = HI(TBUFCTL); \
75 preg.H = HI(TBUFCTL); \
83 preg.H = HI(TBUFCTL); \
Dentry.h43 preg.h = HI(CHIPID); \
116 P0.H = HI(ILAT); \
146 P0.H = HI(ILAT); \
Dblackfin.h56 #define HI(con32) (((con32) >> 16) & 0xFFFF) macro
/arch/mips/pci/
Dops-nile4.c13 #define HI(reg) (reg / 4 + 1) macro
48 vrc_pciregs[HI(NILE4_PCIERR)] = 0; in nile4_pcibios_config_access()
66 err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7; in nile4_pcibios_config_access()
/arch/blackfin/mach-common/
Dinterrupt.S168 P0.H = HI(ILAT);
189 R1.H = HI(VEC_HWERR);
201 p0.h = HI(EBIU_ERRMST);
Dcache.S84 p0.H = HI(DSPID);
/arch/mn10300/kernel/
Dkprobes.c93 #define HI (1 << 5) macro
106 /* 0 0 0 0 */ (NE | NC | CC | VC | GE | GT | HI),
108 /* 0 0 1 0 */ (NE | NS | CC | VC | LT | LE | HI),
114 /* 1 0 0 0 */ (NE | NC | CC | VS | LT | LE | HI),
116 /* 1 0 1 0 */ (NE | NS | CC | VS | GE | GT | HI),
/arch/hexagon/lib/
Dmemcpy.S229 mask.h = #HI(0x7fffffff);
242 r31.h = #HI(.Lmemcpy_return); /* set up final return pointer */

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