1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #ifndef __ASM_CACHETYPE_H 17 #define __ASM_CACHETYPE_H 18 19 #include <asm/cputype.h> 20 21 #define CTR_L1IP_SHIFT 14 22 #define CTR_L1IP_MASK 3 23 24 #define ICACHE_POLICY_RESERVED 0 25 #define ICACHE_POLICY_AIVIVT 1 26 #define ICACHE_POLICY_VIPT 2 27 #define ICACHE_POLICY_PIPT 3 28 icache_policy(void)29static inline u32 icache_policy(void) 30 { 31 return (read_cpuid_cachetype() >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK; 32 } 33 34 /* 35 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is 36 * permitted in the I-cache. 37 */ icache_is_aliasing(void)38static inline int icache_is_aliasing(void) 39 { 40 return icache_policy() != ICACHE_POLICY_PIPT; 41 } 42 icache_is_aivivt(void)43static inline int icache_is_aivivt(void) 44 { 45 return icache_policy() == ICACHE_POLICY_AIVIVT; 46 } 47 48 #endif /* __ASM_CACHETYPE_H */ 49