| /arch/c6x/lib/ |
| D | csum_64plus.S | 54 || ADD .L1 A16,A9,A9
67 || MVK .L1 1,A2
77 ADD .L1 A16,A9,A9
80 || ADD .L1 A8,A9,A9
87 ZERO .L1 A7
119 || ZERO .L1 A7
207 || ADD .L1 A3,A5,A5
297 MV .L1 A0,A3
314 MVK .L1 2,A0
315 AND .L1 A4,A0,A0
[all …]
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| D | memcpy_64plus.S | 16 AND .L1 0x1,A6,A0
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| /arch/arm/mm/ |
| D | proc-xsc3.S | 71 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
176 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
199 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
200 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
227 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
232 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
248 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
253 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
272 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
[all …]
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| /arch/blackfin/ |
| D | Kconfig | 743 bool "Locate interrupt entry code in L1 Memory"
748 into L1 instruction memory. (less latency)
751 …bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memor…
756 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
760 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
765 into L1 instruction memory. (less latency)
768 bool "Locate frequently called timer_interrupt() function in L1 Memory"
773 into L1 instruction memory. (less latency)
776 bool "Locate frequently idle function in L1 Memory"
781 into L1 instruction memory. (less latency)
[all …]
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| /arch/powerpc/boot/dts/ |
| D | sbc8548-pre.dtsi | 38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
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| D | amigaone.dts | 31 d-cache-size = <32768>; // L1, 32K
32 i-cache-size = <32768>; // L1, 32K
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| D | gef_sbc610.dts | 46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
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| D | tqm8xx.dts | 37 d-cache-size = <0x1000>; // L1, 4K
38 i-cache-size = <0x1000>; // L1, 4K
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| D | tqm5200.dts | 31 d-cache-size = <0x4000>; // L1, 16K
32 i-cache-size = <0x4000>; // L1, 16K
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| /arch/hexagon/lib/ |
| D | memset.S | 172 if (r2==#0) jump:nt .L1
199 if (p1) jump .L1
210 if (p0.new) jump:nt .L1
221 if (p0.new) jump:nt .L1
297 .L1: label
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| /arch/c6x/kernel/ |
| D | head.S | 61 CMPEQ .L1 A10,A0,A0
84 L1: BNOP .S2 L1,5 label
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| /arch/m68k/lib/ |
| D | divsi3.S | 98 jpl L1
105 L1: movel sp@(8), d0 /* d0 = dividend */ label
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| D | udivsi3.S | 149 L1: addl d0,d0 | shift reg pair (p,a) one bit left label
157 jcc L1
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| /arch/alpha/boot/ |
| D | main.c | 60 #define L1 ((unsigned long *) 0x200802000) macro
72 pcb_va->ptbr = L1[1] >> 32; in pal_init()
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| D | bootp.c | 65 #define L1 ((unsigned long *) 0x200802000) macro
77 pcb_va->ptbr = L1[1] >> 32; in pal_init()
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| D | bootpz.c | 113 #define L1 ((unsigned long *) 0x200802000) macro
125 pcb_va->ptbr = L1[1] >> 32; in pal_init()
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| /arch/blackfin/kernel/cplb-nompu/ |
| D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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| /arch/blackfin/kernel/cplb-mpu/ |
| D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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| /arch/m68k/fpsp040/ |
| D | setox.S | 104 | 3.1 R := X + N*L1, where L1 := single-precision(-log2/64).
105 | 3.2 R := R + N*L2, L2 := extended-precision(-log2/64 - L1).
106 | Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate
108 | b) N*L1 is exact because N is no longer than 22 bits and
109 | L1 is no longer than 24 bits.
110 | c) The calculation X+N*L1 is also exact due to cancellation.
111 | Thus, R is practically X+N(L1+L2) to full 64 bits.
505 fmuls #0xBC317218,%fp0 | ...N * L1, L1 = lead(-log2/64)
506 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
507 faddx %fp1,%fp0 | ...X + N*L1
[all …]
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| /arch/metag/tbx/ |
| D | tbidspram.S | 43 $L1:
50 BR $L1
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| /arch/blackfin/mach-common/ |
| D | arch_checks.c | 65 # error You need IFLUSH in L1 inst while Anomaly 05000491 applies
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| /arch/arm/mach-s5p64x0/ |
| D | clock.c | 65 L1 = 266*1000, enumerator
72 {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
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| /arch/arm/mach-omap2/ |
| D | sram242x.S | 53 str r3, [r2] @ go to L1-freq operation
56 mov r9, #0x1 @ set up for L1 voltage call
115 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
119 str r5, [r4] @ Force transition to L1
210 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
214 str r8, [r10] @ Force transition to L1
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| D | sram243x.S | 53 str r3, [r2] @ go to L1-freq operation
56 mov r9, #0x1 @ set up for L1 voltage call
115 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
119 str r5, [r4] @ Force transition to L1
210 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
214 str r8, [r10] @ Force transition to L1
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| /arch/arc/kernel/ |
| D | entry.S | 200 ; if L2 IRQ interrupted a L1 ISR, disable preemption
204 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
702 ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
720 ; if L2 IRQ interrupted a L1 ISR, we'd disbaled preemption earlier
730 bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal
|