| /arch/mips/mm/ |
| D | cm3-l2-init.S | 30 # L2 Cache initialization routine
32 # Check L2 cache size
35 # Isolate L2 Line Size
38 # Skip ahead if No L2
44 sllv $11, $14, $11 # Now have true L2 line size in bytes
46 # Isolate L2 Sets per Way
49 sllv $12, $14, $12 # L2 Sets per way
51 # Isolate L2 Associativity
52 # L2 Assoc (-1)
77 # L2 Index Store Tag Cache Op
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| /arch/mips/cavium-octeon/ |
| D | Kconfig | 45 bool "Lock often used kernel code in the L2"
48 Enable locking parts of the kernel into the L2 cache.
51 bool "Lock the TLB handler in L2"
55 Lock the low level TLB fast path into L2.
58 bool "Lock the exception handler in L2"
62 Lock the low level exception handler into L2.
65 bool "Lock the interrupt handler in L2"
69 Lock the low level interrupt handler into L2.
72 bool "Lock the 2nd level interrupt handler in L2"
76 Lock the 2nd level interrupt handler in L2.
[all …]
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| /arch/arm/boot/dts/ |
| D | highbank.dts | 37 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
65 next-level-cache = <&L2>;
74 next-level-cache = <&L2>;
113 L2: l2-cache { label
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| D | vexpress-v2p-ca9.dts | 40 next-level-cache = <&L2>;
47 next-level-cache = <&L2>;
54 next-level-cache = <&L2>;
61 next-level-cache = <&L2>;
138 L2: cache-controller@1e00a000 { label
196 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
241 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
255 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
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| D | imx6q.dtsi | 22 next-level-cache = <&L2>;
43 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
55 next-level-cache = <&L2>;
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| D | vexpress-v2p-ca5s.dts | 40 next-level-cache = <&L2>;
47 next-level-cache = <&L2>;
106 L2: cache-controller@2c0f0000 { label
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| /arch/c6x/kernel/ |
| D | head.S | 24 SUB .L2 B6,B5,B6 ; bss size
33 ZERO .L2 B13
34 ZERO .L2 B12
38 CMPLT .L2 B0,0,B1
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| /arch/powerpc/boot/dts/fsl/ |
| D | b4860si-pre.dtsi | 65 next-level-cache = <&L2>;
70 next-level-cache = <&L2>;
75 next-level-cache = <&L2>;
80 next-level-cache = <&L2>;
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| /arch/c6x/lib/ |
| D | csum_64plus.S | 57 || ADD .L2 B8,B9,B9
83 CMPGT .L2 B5,0,B0
193 CMPGT .L2 B0,0,B1
293 CMPGT .L2 B4,0,B0
299 || MV .L2 B4,B3
303 [A0] SUB .L2 B3,1,B3
308 SUB .L2 B3,1,B3
319 SUB .L2 B0,1,B0
347 MVK .L2 2,B0
348 AND .L2 B3,B0,B0
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| /arch/powerpc/boot/dts/ |
| D | mpc8572ds_camp_core1.dts | 4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
62 cache-size = <0x80000>; // L2, 512K
84 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
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| D | mpc8572ds_camp_core0.dts | 4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
45 cache-size = <0x80000>; // L2, 512K
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| D | p1020rdb-pc_camp_core1.dts | 4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
106 16 /* ecm, mem, L2, pci0, pci1 */
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| /arch/m68k/lib/ |
| D | divsi3.S | 106 jpl L2
114 L2: movel d1, sp@- label
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| D | udivsi3.S | 153 jcs L2 | if no carry,
156 L2: subql IMM (1),d4 label
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| /arch/score/lib/ |
| D | string.S | 34 ble .L2
40 beq .L2
54 .L2: label
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| /arch/blackfin/kernel/cplb-nompu/ |
| D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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| /arch/blackfin/kernel/cplb-mpu/ |
| D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
|
| /arch/arc/kernel/ |
| D | entry.S | 200 ; if L2 IRQ interrupted a L1 ISR, disable preemption
204 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
702 ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
720 ; if L2 IRQ interrupted a L1 ISR, we'd disbaled preemption earlier
723 ; things to what they were, before returning from L2 context
727 brne r9, orig_r8_IS_IRQ2, 149f ; infact a L2 ISR ret path
730 bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal
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| /arch/sh/lib/ |
| D | __clear_user.S | 81 .L2: dt r3 define
83 bf/s .L2
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| /arch/alpha/kernel/ |
| D | setup.c | 1337 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1360 L2 = external_cache_probe(128*1024, 5); in determine_cpu_caches()
1374 L2 = (car & 1 ? CSHAPE (size, 3, 1) : -1); in determine_cpu_caches()
1388 L2 = CSHAPE (96*1024, width, 3); in determine_cpu_caches()
1422 L2 = ((cbox_config >> 31) & 1 ? CSHAPE (size, 6, 1) : -1); in determine_cpu_caches()
1424 L2 = external_cache_probe(512*1024, 6); in determine_cpu_caches()
1436 L2 = external_cache_probe(1024*1024, 6); in determine_cpu_caches()
1443 L2 = CSHAPE(7*1024*1024/4, 6, 7); in determine_cpu_caches()
1449 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1455 alpha_l2_cacheshape = L2; in determine_cpu_caches()
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| /arch/metag/tbx/ |
| D | tbidspram.S | 77 $L2:
84 BR $L2
|
| /arch/arm/mach-omap2/ |
| D | sleep44xx.S | 156 ldreq r0, [r8, #L2X0_SAVE_OFFSET0] @ Retrieve L2 state from SAR
314 ldr r12, =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH
319 ldr r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL
322 ldr r12, =OMAP4_MON_L2X0_CTRL_INDEX @ Enable L2 cache
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| /arch/m68k/fpsp040/ |
| D | setox.S | 105 | 3.2 R := R + N*L2, L2 := extended-precision(-log2/64 - L1).
106 | Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate
111 | Thus, R is practically X+N(L1+L2) to full 64 bits.
498 movew L2,L_SCR1(%a6) | ...prefetch L2, no need in CB
506 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
665 | MOVE.W #$3FDC,L2 ...prefetch L2 in CB mode
672 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
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| /arch/arm/mach-s5p64x0/ |
| D | clock.c | 66 L2 = 133*1000, enumerator
73 {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
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| /arch/arm/mach-tegra/ |
| D | Kconfig | 42 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
59 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
|