Searched refs:L3 (Results 1 – 19 of 19) sorted by relevance
| /arch/m68k/lib/ |
| D | divsi3.S | 120 jpl L3
123 L3: movel sp@+, d2 label
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| D | udivsi3.S | 100 jcc L3 /* then try next algorithm */
112 L3: movel d1, d2 /* use d2 as divisor backup */ label
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| /arch/blackfin/kernel/cplb-nompu/ |
| D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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| /arch/blackfin/kernel/cplb-mpu/ |
| D | Makefile | 8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
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| /arch/metag/tbx/ |
| D | tbidspram.S | 111 $L3:
118 BR $L3
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| /arch/metag/lib/ |
| D | div64.S | 13 BNE $L3
18 $L3:
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| /arch/alpha/kernel/ |
| D | setup.c | 1337 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1348 L3 = -1; in determine_cpu_caches()
1369 L3 = -1; in determine_cpu_caches()
1400 L3 = external_cache_probe(1024*1024, width); in determine_cpu_caches()
1414 L3 = -1; in determine_cpu_caches()
1437 L3 = -1; in determine_cpu_caches()
1444 L3 = -1; in determine_cpu_caches()
1449 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1456 alpha_l3_cacheshape = L3; in determine_cpu_caches()
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| /arch/xtensa/lib/ |
| D | memset.S | 91 bbci.l a4, 2, .L3
95 .L3: label
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| D | usercopy.S | 187 bbci.l a4, 2, .L3
193 .L3: label
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| D | memcopy.S | 177 bbsi.l a4, 2, .L3
181 .L3: label
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| /arch/x86/kernel/cpu/ |
| D | perf_event_intel_ds.c | 54 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
58 OP_LH | P(LVL, L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
59 OP_LH | P(LVL, L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
60 OP_LH | P(LVL, L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
61 OP_LH | P(LVL, L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
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| /arch/hexagon/lib/ |
| D | memset.S | 177 if (p0.new) jump:nt .L3
189 .L3: label
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| /arch/arm/boot/dts/ |
| D | omap5.dtsi | 443 <0x49032000 0x7f>; /* L3 Interconnect */
455 <0x4902e000 0x7f>; /* L3 Interconnect */
466 <0x49022000 0xff>; /* L3 Interconnect */
480 <0x49024000 0xff>; /* L3 Interconnect */
494 <0x49026000 0xff>; /* L3 Interconnect */
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| D | omap4.dtsi | 404 <0x49032000 0x7f>; /* L3 Interconnect */
416 <0x4902e000 0x7f>; /* L3 Interconnect */
427 <0x49022000 0xff>; /* L3 Interconnect */
441 <0x49024000 0xff>; /* L3 Interconnect */
455 <0x49026000 0xff>; /* L3 Interconnect */
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| /arch/blackfin/mach-bf561/ |
| D | secondary.S | 50 L3 = r6; define
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| /arch/arm/mach-omap2/ |
| D | sram242x.S | 100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
194 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
310 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
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| D | sram243x.S | 100 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
194 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
310 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
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| D | Kconfig | 427 can be found on path between MPU to EMIF and MPU to L3 interconnect.
435 In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
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| /arch/blackfin/mach-common/ |
| D | head.S | 59 L3 = r6; define
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