| /arch/metag/lib/ |
| D | lshrdi3.S | 22 LSR D0Re0,D0Re0,D0Ar4 ! LO = LO >> COUNT
26 LSR D1Re0,D1Re0,D1Ar3 ! HI = HI >> COUNT
30 LSR D0Re0,D1Re0,D1Ar3 ! LO = HI >> N
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| D | memmove.S | 43 LSR D1Ar5, D1Ar3, #3
76 LSR D1Ar5, D1Ar3, #3
118 LSR D0Re0, D0Re0, D0.6
126 LSR D0Re0, D0Re0, D0.6
155 LSR D0Re0, D0Re0, D0.6
163 LSR D0Re0, D0Re0, D0.6
211 LSR D1Ar5, D1Ar3, #3
241 LSR D1Ar5, D1Ar3, #3
272 LSR D0Re0, D0Re0, D0.6
279 LSR D0.5, D0.5, D0.6 define
[all …]
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| D | ip_fast_csum.S | 22 LSR D0Ar4,D0Re0,#16
26 LSR D0Ar4,D0Re0,#16
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| D | div64.S | 59 LSR D0Re0,D0Re0,#1
60 LSR D1Re0,D1Re0,#1
63 LSR D0Ar4,D0Ar4,#1
64 LSR D1Ar3,D1Ar3,#1
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| D | muldi3.S | 26 LSR D1Ar5,D0Ar6,#16
38 LSR D1Ar5,D0Ar6,#16
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| D | memcpy.S | 53 LSR D1Ar5, D1Ar3, #3 ! D1Ar5 = number of 8 byte blocks
120 LSR D0Re0, D0Re0, D0Ar6
125 LSR D0Ar2, D0Ar2, D0Ar6
145 LSR D0Re0, D0Re0, D0Ar6
149 LSR D0FrT, D0Ar2, D0Ar6
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| D | ashrdi3.S | 22 LSR D0Re0,D0Re0,D0Ar4 ! LO = LO >> COUNT
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| D | ashldi3.S | 22 LSR D0Ar6,D0Re0,D0Ar4 ! TMP= LO >> -(COUNT - 32)
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| D | divsi3.S | 38 LSR D1Ar3,D1Ar1,#2 ! Calculate (Au & (~3)) >> 2
94 LSR D1Re0, D1Re0, #1 ! Shift down B
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| /arch/powerpc/platforms/wsp/ |
| D | h8.c | 26 #define LSR 5 /* Line Status Register */ macro
34 lsr = readb(h8 + LSR); in wsp_h8_putc()
44 lsr = readb(h8 + LSR); in wsp_h8_getc()
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| /arch/metag/tbx/ |
| D | tbidspram.S | 40 LSR D1Ar1, D1Ar1, #_TBIECH_DSPRAM_DUA_S
74 LSR D1Ar1, D1Ar1, #_TBIECH_DSPRAM_DUB_S
108 LSR D1Ar1, D1Ar1, #_TBIECH_DSPRAM_DUA_S
142 LSR D1Ar1, D1Ar1, #_TBIECH_DSPRAM_DUB_S
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| D | tbipcx.S | 184 LSR D1Ar3,D1Ar3,#TXDIVTIME_IRQENC_S
314 LSR D1Ar3,D1Ar3,#TXENABLE_THREAD_S-2
335 LSR D1Ar3,D1Ar3,#TXENABLE_THREAD_S-2
370 LSR D1Ar3,D0Re0,#TXSTATUS_MAJOR_HALT_S
379 LSR D1Ar3,D1Ar1,#1 /* Shift needed for MINIM paths (fill stall) */
407 LSR D1Ar3,D1Ar5,#22 /* Convert into signal number */
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| D | tbictxfpu.S | 63 LSR D0Re0, D0Ar6, #8
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| /arch/frv/kernel/ |
| D | gdb-io.c | 38 } while (!(__UART(LSR) & UART_LSR_##STATE))
118 while (__UART(LSR) & UART_LSR_DR) { in gdbstub_do_rx()
123 gdbstub_rx_buffer[ix++] = __UART(LSR); in gdbstub_do_rx()
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| D | debug-stub.c | 31 } while (!(__UART0(LSR) & UART_LSR_##STATE))
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| /arch/x86/boot/ |
| D | tty.c | 23 #define LSR 5 /* Line Status */ macro
34 while ((inb(early_serial_base + LSR) & XMTRDY) == 0 && --timeout) in serial_putchar()
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| D | early_serial_console.c | 16 #define LSR 5 /* Line Status */ macro
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| /arch/arm/mm/ |
| D | abort-ev7.S | 47 orr r1, r1, ip, LSR #1
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| D | abort-lv4t.S | 132 mov r6, r6, lsr r9 @ 4: LSR #!0
134 mov r6, r6, lsr #32 @ 5: LSR #32
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| /arch/x86/kernel/ |
| D | early_printk.c | 90 #define LSR 5 /* Line Status */ macro
99 while ((inb(early_serial_base + LSR) & XMTRDY) == 0 && --timeout) in early_serial_putc()
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| /arch/arm/mach-orion5x/ |
| D | terastation_pro2-setup.c | 173 while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) { in tsp2_miconread()
193 while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE)) in tsp2_miconwrite()
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| D | kurobox_pro-setup.c | 194 while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) { in kurobox_pro_miconread()
214 while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE)) in kurobox_pro_miconwrite()
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| /arch/x86/boot/compressed/ |
| D | misc.c | 160 #define LSR 5 /* Line Status */ macro
165 while ((inb(early_serial_base + LSR) & XMTRDY) == 0 && --timeout) in serial_putchar()
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| /arch/metag/kernel/ |
| D | user_gateway.S | 43 LSR D1Ar3,D1Ar3,#(TXENABLE_THREAD_S - 2)
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| /arch/arm/include/debug/ |
| D | omap2plus.S | 175 orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset
178 orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR)
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