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Searched refs:MIPS_CACHE_SYNC_WAR (Results 1 – 25 of 36) sorted by relevance

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/arch/mips/include/asm/
Dwar.h196 #ifndef MIPS_CACHE_SYNC_WAR
197 #error Check setting of MIPS_CACHE_SYNC_WAR for your platform
/arch/mips/include/asm/mach-jazz/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-sead3/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 1 macro
/arch/mips/include/asm/mach-ip27/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-pnx833x/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-netlogic/
Dwar.h19 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-loongson/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-lantiq/
Dwar.h17 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-ar7/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-ip32/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-rc32434/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-malta/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 1 macro
/arch/mips/include/asm/mach-emma2rh/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-powertv/
Dwar.h21 #define MIPS_CACHE_SYNC_WAR 1 macro
/arch/mips/include/asm/mach-bcm47xx/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-cavium-octeon/
Dwar.h19 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-bcm63xx/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-tx49xx/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-cobalt/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-rm/
Dwar.h22 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-dec/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-au1x00/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-loongson1/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-ip22/
Dwar.h22 #define MIPS_CACHE_SYNC_WAR 0 macro
/arch/mips/include/asm/mach-ath79/
Dwar.h18 #define MIPS_CACHE_SYNC_WAR 0 macro

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