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Searched refs:MSC1 (Results 1 – 8 of 8) sorted by relevance

/arch/arm/mach-pxa/
Dsmemc.c22 msc[1] = __raw_readl(MSC1); in pxa3xx_smemc_suspend()
36 __raw_writel(msc[1], MSC1); in pxa3xx_smemc_resume()
Dxcep.c173 __raw_writel((__raw_readl(MSC1) & 0xffff) | 0xD5540000, MSC1); in xcep_init()
Dh5000.c178 __raw_writel(0x7ff424fa, MSC1); in fix_msc()
Dcm-x2xx.c399 sleep_save_msc[1] = __raw_readl(MSC1); in cmx2xx_suspend()
423 __raw_writel(sleep_save_msc[1], MSC1); in cmx2xx_resume()
Dzeus.c835 msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc; in zeus_init()
837 __raw_writel(msc1, MSC1); in zeus_init()
/arch/arm/mach-pxa/include/mach/
Dsmemc.h21 #define MSC1 (SMEMC_VIRT + 0x0C) /* Static Memory Control Register 1 */ macro
/arch/arm/mach-sa1100/
Dsleep.S82 ldr r1, =MSC1
/arch/arm/mach-sa1100/include/mach/
DSA-1100.h1477 #define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */ macro