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Searched refs:MX51_AIPS2_BASE_ADDR (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-imx/
Dmx51.h73 #define MX51_AIPS2_BASE_ADDR 0x83f00000 macro
76 #define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000)
77 #define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000)
78 #define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000)
79 #define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000)
80 #define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000)
81 #define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000)
82 #define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000)
83 #define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000)
84 #define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000)
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Dmm-imx5.c147 imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR)); in imx51_soc_init()