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Searched refs:OCP_MOD (Results 1 – 7 of 7) sorted by relevance

/arch/arm/mach-omap2/
Dprm2xxx.h39 #define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
41 #define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
44 #define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
46 #define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
49 #define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
51 #define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
53 #define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
55 #define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
57 #define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
59 #define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
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Dprm3xxx.c95 irqstatus = omap2_prm_read_mod_reg(OCP_MOD, in omap3_prm_vp_check_txdone()
105 OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); in omap3_prm_vp_clear_txdone()
151 mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); in omap3xxx_prm_read_pending_irqs()
152 st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); in omap3xxx_prm_read_pending_irqs()
167 omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET); in omap3xxx_prm_ocp_barrier()
183 saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD, in omap3xxx_prm_save_and_clear_irqen()
185 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); in omap3xxx_prm_save_and_clear_irqen()
188 omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET); in omap3xxx_prm_save_and_clear_irqen()
203 omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD, in omap3xxx_prm_restore_irqen()
Dcm3xxx.h32 #define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
33 #define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
34 #define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
Dpm24xx.c124 l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); in omap2_enter_full_retention()
126 omap2_prm_write_mod_reg(0x01, OCP_MOD, in omap2_enter_full_retention()
129 omap2_prm_write_mod_reg(0x20, OCP_MOD, in omap2_enter_full_retention()
133 omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); in omap2_enter_full_retention()
225 omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, in prcm_setup_regs()
281 l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); in omap2_pm_init()
Dprm3xxx.h37 #define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
39 #define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
42 #define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
44 #define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
Dprcm-common.h25 #define OCP_MOD 0x000 macro
34 #define OMAP24XX_GR_MOD OCP_MOD
Dpm34xx.c547 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); in prcm_setup_regs()