| /arch/arm/mach-msm/ |
| D | devices-msm7x30.c | 168 CLK_PCOM("camif_pad_pclk", CAMIF_PAD_P_CLK, NULL, OFF),
173 CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX),
174 CLK_PCOM("emdh_pclk", EMDH_P_CLK, NULL, OFF),
182 CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
183 CLK_PCOM("jpeg_clk", JPEG_CLK, NULL, OFF),
184 CLK_PCOM("jpeg_pclk", JPEG_P_CLK, NULL, OFF),
189 CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX),
191 CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
208 CLK_PCOM("rotator_imem_clk", ROTATOR_IMEM_CLK, NULL, OFF),
209 CLK_PCOM("rotator_pclk", ROTATOR_P_CLK, NULL, OFF),
[all …]
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| D | devices-qsd8x50.c | 331 CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX),
337 CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
339 CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX),
340 CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
346 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
347 CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF),
348 CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF),
349 CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF),
350 CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF),
351 CLK_PCOM("sdc_clk", SDC3_CLK, "msm_sdcc.3", OFF),
[all …]
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| D | devices-msm7x00.c | 434 CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF),
436 CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, OFF),
440 CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
442 CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
445 CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX),
446 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
447 CLK_PCOM("sdc_clk", SDC1_CLK, "msm_sdcc.1", OFF),
448 CLK_PCOM("sdc_pclk", SDC1_P_CLK, "msm_sdcc.1", OFF),
449 CLK_PCOM("sdc_clk", SDC2_CLK, "msm_sdcc.2", OFF),
450 CLK_PCOM("sdc_pclk", SDC2_P_CLK, "msm_sdcc.2", OFF),
[all …]
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| D | clock.h | 59 #define OFF CLKFLAG_AUTO_OFF macro
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| /arch/arm64/kernel/ |
| D | hw_breakpoint.c | 81 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \ argument
82 case (OFF + N): \
86 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \ argument
87 case (OFF + N): \
91 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \ argument
92 READ_WB_REG_CASE(OFF, 0, REG, VAL); \
93 READ_WB_REG_CASE(OFF, 1, REG, VAL); \
94 READ_WB_REG_CASE(OFF, 2, REG, VAL); \
95 READ_WB_REG_CASE(OFF, 3, REG, VAL); \
96 READ_WB_REG_CASE(OFF, 4, REG, VAL); \
[all …]
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| /arch/mn10300/include/asm/ |
| D | cache.h | 45 #define ICACHE_DATA(WAY, ENTRY, OFF) \ argument
47 (ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32)
53 #define DCACHE_DATA(WAY, ENTRY, OFF) \ argument
55 (ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32)
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| /arch/powerpc/platforms/pseries/ |
| D | eeh_pe.c | 577 #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF)) in eeh_restore_one_device_bars() argument
578 #define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)]) in eeh_restore_one_device_bars() argument
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| /arch/sparc/net/ |
| D | bpf_jit_comp.c | 237 #define emit_ldmem(OFF, DEST) \ argument
238 do { *prog++ = LD32I | RS1(FP) | S13(-(OFF)) | RD(DEST); \
241 #define emit_stmem(OFF, SRC) \ argument
242 do { *prog++ = LD32I | RS1(FP) | S13(-(OFF)) | RD(SRC); \
283 #define emit_branch_off(BR_OPC, OFF) \ argument
284 do { *prog++ = BR_OPC | WDISP22(OFF); \
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| /arch/arm/mach-omap2/ |
| D | sleep34xx.S | 417 cmp r4, #0x0 @ Check if previous power state of CORE is OFF
437 cmp r2, #0x0 @ Check if previous power state of CORE is OFF
455 cmp r2, #0x0 @ Check if target power state was OFF or RET
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| /arch/arm/mach-omap1/ |
| D | board-osk.c | 216 tps65010_set_led(LED2, OFF); in osk_tps_setup()
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| /arch/m32r/kernel/ |
| D | head.S | 210 st r5, @r4 ; Set MATM Reg(T bit OFF)
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| /arch/m32r/platforms/mappi/ |
| D | dot.gdbinit.nommu | 41 # LED OFF
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| D | dot.gdbinit | 41 # LED OFF
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| D | dot.gdbinit.smp | 104 # LED OFF
|