1 #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H 2 #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H 3 4 /* 5 * OMAP2/3 PRCM base and module definitions 6 * 7 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc. 8 * Copyright (C) 2007-2009 Nokia Corporation 9 * 10 * Written by Paul Walmsley 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17 /* Module offsets from both CM_BASE & PRM_BASE */ 18 19 /* 20 * Offsets that are the same on 24xx and 34xx 21 * 22 * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is 23 * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2. 24 */ 25 #define OCP_MOD 0x000 26 #define MPU_MOD 0x100 27 #define CORE_MOD 0x200 28 #define GFX_MOD 0x300 29 #define WKUP_MOD 0x400 30 #define PLL_MOD 0x500 31 32 33 /* Chip-specific module offsets */ 34 #define OMAP24XX_GR_MOD OCP_MOD 35 #define OMAP24XX_DSP_MOD 0x800 36 37 #define OMAP2430_MDM_MOD 0xc00 38 39 /* IVA2 module is < base on 3430 */ 40 #define OMAP3430_IVA2_MOD -0x800 41 #define OMAP3430ES2_SGX_MOD GFX_MOD 42 #define OMAP3430_CCR_MOD PLL_MOD 43 #define OMAP3430_DSS_MOD 0x600 44 #define OMAP3430_CAM_MOD 0x700 45 #define OMAP3430_PER_MOD 0x800 46 #define OMAP3430_EMU_MOD 0x900 47 #define OMAP3430_GR_MOD 0xa00 48 #define OMAP3430_NEON_MOD 0xb00 49 #define OMAP3430ES2_USBHOST_MOD 0xc00 50 51 /* 24XX register bits shared between CM & PRM registers */ 52 53 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 54 #define OMAP2420_EN_MMC_SHIFT 26 55 #define OMAP2420_EN_MMC_MASK (1 << 26) 56 #define OMAP24XX_EN_UART2_SHIFT 22 57 #define OMAP24XX_EN_UART2_MASK (1 << 22) 58 #define OMAP24XX_EN_UART1_SHIFT 21 59 #define OMAP24XX_EN_UART1_MASK (1 << 21) 60 #define OMAP24XX_EN_MCSPI2_SHIFT 18 61 #define OMAP24XX_EN_MCSPI2_MASK (1 << 18) 62 #define OMAP24XX_EN_MCSPI1_SHIFT 17 63 #define OMAP24XX_EN_MCSPI1_MASK (1 << 17) 64 #define OMAP24XX_EN_MCBSP2_SHIFT 16 65 #define OMAP24XX_EN_MCBSP2_MASK (1 << 16) 66 #define OMAP24XX_EN_MCBSP1_SHIFT 15 67 #define OMAP24XX_EN_MCBSP1_MASK (1 << 15) 68 #define OMAP24XX_EN_GPT12_SHIFT 14 69 #define OMAP24XX_EN_GPT12_MASK (1 << 14) 70 #define OMAP24XX_EN_GPT11_SHIFT 13 71 #define OMAP24XX_EN_GPT11_MASK (1 << 13) 72 #define OMAP24XX_EN_GPT10_SHIFT 12 73 #define OMAP24XX_EN_GPT10_MASK (1 << 12) 74 #define OMAP24XX_EN_GPT9_SHIFT 11 75 #define OMAP24XX_EN_GPT9_MASK (1 << 11) 76 #define OMAP24XX_EN_GPT8_SHIFT 10 77 #define OMAP24XX_EN_GPT8_MASK (1 << 10) 78 #define OMAP24XX_EN_GPT7_SHIFT 9 79 #define OMAP24XX_EN_GPT7_MASK (1 << 9) 80 #define OMAP24XX_EN_GPT6_SHIFT 8 81 #define OMAP24XX_EN_GPT6_MASK (1 << 8) 82 #define OMAP24XX_EN_GPT5_SHIFT 7 83 #define OMAP24XX_EN_GPT5_MASK (1 << 7) 84 #define OMAP24XX_EN_GPT4_SHIFT 6 85 #define OMAP24XX_EN_GPT4_MASK (1 << 6) 86 #define OMAP24XX_EN_GPT3_SHIFT 5 87 #define OMAP24XX_EN_GPT3_MASK (1 << 5) 88 #define OMAP24XX_EN_GPT2_SHIFT 4 89 #define OMAP24XX_EN_GPT2_MASK (1 << 4) 90 #define OMAP2420_EN_VLYNQ_SHIFT 3 91 #define OMAP2420_EN_VLYNQ_MASK (1 << 3) 92 93 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ 94 #define OMAP2430_EN_GPIO5_SHIFT 10 95 #define OMAP2430_EN_GPIO5_MASK (1 << 10) 96 #define OMAP2430_EN_MCSPI3_SHIFT 9 97 #define OMAP2430_EN_MCSPI3_MASK (1 << 9) 98 #define OMAP2430_EN_MMCHS2_SHIFT 8 99 #define OMAP2430_EN_MMCHS2_MASK (1 << 8) 100 #define OMAP2430_EN_MMCHS1_SHIFT 7 101 #define OMAP2430_EN_MMCHS1_MASK (1 << 7) 102 #define OMAP24XX_EN_UART3_SHIFT 2 103 #define OMAP24XX_EN_UART3_MASK (1 << 2) 104 #define OMAP24XX_EN_USB_SHIFT 0 105 #define OMAP24XX_EN_USB_MASK (1 << 0) 106 107 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ 108 #define OMAP2430_EN_MDM_INTC_SHIFT 11 109 #define OMAP2430_EN_MDM_INTC_MASK (1 << 11) 110 #define OMAP2430_EN_USBHS_SHIFT 6 111 #define OMAP2430_EN_USBHS_MASK (1 << 6) 112 #define OMAP24XX_EN_GPMC_SHIFT 1 113 #define OMAP24XX_EN_GPMC_MASK (1 << 1) 114 115 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ 116 #define OMAP2420_ST_MMC_SHIFT 26 117 #define OMAP2420_ST_MMC_MASK (1 << 26) 118 #define OMAP24XX_ST_UART2_SHIFT 22 119 #define OMAP24XX_ST_UART2_MASK (1 << 22) 120 #define OMAP24XX_ST_UART1_SHIFT 21 121 #define OMAP24XX_ST_UART1_MASK (1 << 21) 122 #define OMAP24XX_ST_MCSPI2_SHIFT 18 123 #define OMAP24XX_ST_MCSPI2_MASK (1 << 18) 124 #define OMAP24XX_ST_MCSPI1_SHIFT 17 125 #define OMAP24XX_ST_MCSPI1_MASK (1 << 17) 126 #define OMAP24XX_ST_MCBSP2_SHIFT 16 127 #define OMAP24XX_ST_MCBSP2_MASK (1 << 16) 128 #define OMAP24XX_ST_MCBSP1_SHIFT 15 129 #define OMAP24XX_ST_MCBSP1_MASK (1 << 15) 130 #define OMAP24XX_ST_GPT12_SHIFT 14 131 #define OMAP24XX_ST_GPT12_MASK (1 << 14) 132 #define OMAP24XX_ST_GPT11_SHIFT 13 133 #define OMAP24XX_ST_GPT11_MASK (1 << 13) 134 #define OMAP24XX_ST_GPT10_SHIFT 12 135 #define OMAP24XX_ST_GPT10_MASK (1 << 12) 136 #define OMAP24XX_ST_GPT9_SHIFT 11 137 #define OMAP24XX_ST_GPT9_MASK (1 << 11) 138 #define OMAP24XX_ST_GPT8_SHIFT 10 139 #define OMAP24XX_ST_GPT8_MASK (1 << 10) 140 #define OMAP24XX_ST_GPT7_SHIFT 9 141 #define OMAP24XX_ST_GPT7_MASK (1 << 9) 142 #define OMAP24XX_ST_GPT6_SHIFT 8 143 #define OMAP24XX_ST_GPT6_MASK (1 << 8) 144 #define OMAP24XX_ST_GPT5_SHIFT 7 145 #define OMAP24XX_ST_GPT5_MASK (1 << 7) 146 #define OMAP24XX_ST_GPT4_SHIFT 6 147 #define OMAP24XX_ST_GPT4_MASK (1 << 6) 148 #define OMAP24XX_ST_GPT3_SHIFT 5 149 #define OMAP24XX_ST_GPT3_MASK (1 << 5) 150 #define OMAP24XX_ST_GPT2_SHIFT 4 151 #define OMAP24XX_ST_GPT2_MASK (1 << 4) 152 #define OMAP2420_ST_VLYNQ_SHIFT 3 153 #define OMAP2420_ST_VLYNQ_MASK (1 << 3) 154 155 /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ 156 #define OMAP2430_ST_MDM_INTC_SHIFT 11 157 #define OMAP2430_ST_MDM_INTC_MASK (1 << 11) 158 #define OMAP2430_ST_GPIO5_SHIFT 10 159 #define OMAP2430_ST_GPIO5_MASK (1 << 10) 160 #define OMAP2430_ST_MCSPI3_SHIFT 9 161 #define OMAP2430_ST_MCSPI3_MASK (1 << 9) 162 #define OMAP2430_ST_MMCHS2_SHIFT 8 163 #define OMAP2430_ST_MMCHS2_MASK (1 << 8) 164 #define OMAP2430_ST_MMCHS1_SHIFT 7 165 #define OMAP2430_ST_MMCHS1_MASK (1 << 7) 166 #define OMAP2430_ST_USBHS_SHIFT 6 167 #define OMAP2430_ST_USBHS_MASK (1 << 6) 168 #define OMAP24XX_ST_UART3_SHIFT 2 169 #define OMAP24XX_ST_UART3_MASK (1 << 2) 170 #define OMAP24XX_ST_USB_SHIFT 0 171 #define OMAP24XX_ST_USB_MASK (1 << 0) 172 173 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 174 #define OMAP24XX_EN_GPIOS_SHIFT 2 175 #define OMAP24XX_EN_GPIOS_MASK (1 << 2) 176 #define OMAP24XX_EN_GPT1_SHIFT 0 177 #define OMAP24XX_EN_GPT1_MASK (1 << 0) 178 179 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ 180 #define OMAP24XX_ST_GPIOS_SHIFT 2 181 #define OMAP24XX_ST_GPIOS_MASK (1 << 2) 182 #define OMAP24XX_ST_32KSYNC_SHIFT 1 183 #define OMAP24XX_ST_32KSYNC_MASK (1 << 1) 184 #define OMAP24XX_ST_GPT1_SHIFT 0 185 #define OMAP24XX_ST_GPT1_MASK (1 << 0) 186 187 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ 188 #define OMAP2430_ST_MDM_SHIFT 0 189 #define OMAP2430_ST_MDM_MASK (1 << 0) 190 191 192 /* 3430 register bits shared between CM & PRM registers */ 193 194 /* CM_REVISION, PRM_REVISION shared bits */ 195 #define OMAP3430_REV_SHIFT 0 196 #define OMAP3430_REV_MASK (0xff << 0) 197 198 /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */ 199 #define OMAP3430_AUTOIDLE_MASK (1 << 0) 200 201 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 202 #define OMAP3430_EN_MMC3_MASK (1 << 30) 203 #define OMAP3430_EN_MMC3_SHIFT 30 204 #define OMAP3430_EN_MMC2_MASK (1 << 25) 205 #define OMAP3430_EN_MMC2_SHIFT 25 206 #define OMAP3430_EN_MMC1_MASK (1 << 24) 207 #define OMAP3430_EN_MMC1_SHIFT 24 208 #define AM35XX_EN_UART4_MASK (1 << 23) 209 #define AM35XX_EN_UART4_SHIFT 23 210 #define OMAP3430_EN_MCSPI4_MASK (1 << 21) 211 #define OMAP3430_EN_MCSPI4_SHIFT 21 212 #define OMAP3430_EN_MCSPI3_MASK (1 << 20) 213 #define OMAP3430_EN_MCSPI3_SHIFT 20 214 #define OMAP3430_EN_MCSPI2_MASK (1 << 19) 215 #define OMAP3430_EN_MCSPI2_SHIFT 19 216 #define OMAP3430_EN_MCSPI1_MASK (1 << 18) 217 #define OMAP3430_EN_MCSPI1_SHIFT 18 218 #define OMAP3430_EN_I2C3_MASK (1 << 17) 219 #define OMAP3430_EN_I2C3_SHIFT 17 220 #define OMAP3430_EN_I2C2_MASK (1 << 16) 221 #define OMAP3430_EN_I2C2_SHIFT 16 222 #define OMAP3430_EN_I2C1_MASK (1 << 15) 223 #define OMAP3430_EN_I2C1_SHIFT 15 224 #define OMAP3430_EN_UART2_MASK (1 << 14) 225 #define OMAP3430_EN_UART2_SHIFT 14 226 #define OMAP3430_EN_UART1_MASK (1 << 13) 227 #define OMAP3430_EN_UART1_SHIFT 13 228 #define OMAP3430_EN_GPT11_MASK (1 << 12) 229 #define OMAP3430_EN_GPT11_SHIFT 12 230 #define OMAP3430_EN_GPT10_MASK (1 << 11) 231 #define OMAP3430_EN_GPT10_SHIFT 11 232 #define OMAP3430_EN_MCBSP5_MASK (1 << 10) 233 #define OMAP3430_EN_MCBSP5_SHIFT 10 234 #define OMAP3430_EN_MCBSP1_MASK (1 << 9) 235 #define OMAP3430_EN_MCBSP1_SHIFT 9 236 #define OMAP3430_EN_FSHOSTUSB_MASK (1 << 5) 237 #define OMAP3430_EN_FSHOSTUSB_SHIFT 5 238 #define OMAP3430_EN_D2D_MASK (1 << 3) 239 #define OMAP3430_EN_D2D_SHIFT 3 240 241 /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 242 #define OMAP3430_EN_HSOTGUSB_MASK (1 << 4) 243 #define OMAP3430_EN_HSOTGUSB_SHIFT 4 244 245 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ 246 #define OMAP3430_ST_MMC3_SHIFT 30 247 #define OMAP3430_ST_MMC3_MASK (1 << 30) 248 #define OMAP3430_ST_MMC2_SHIFT 25 249 #define OMAP3430_ST_MMC2_MASK (1 << 25) 250 #define OMAP3430_ST_MMC1_SHIFT 24 251 #define OMAP3430_ST_MMC1_MASK (1 << 24) 252 #define OMAP3430_ST_MCSPI4_SHIFT 21 253 #define OMAP3430_ST_MCSPI4_MASK (1 << 21) 254 #define OMAP3430_ST_MCSPI3_SHIFT 20 255 #define OMAP3430_ST_MCSPI3_MASK (1 << 20) 256 #define OMAP3430_ST_MCSPI2_SHIFT 19 257 #define OMAP3430_ST_MCSPI2_MASK (1 << 19) 258 #define OMAP3430_ST_MCSPI1_SHIFT 18 259 #define OMAP3430_ST_MCSPI1_MASK (1 << 18) 260 #define OMAP3430_ST_I2C3_SHIFT 17 261 #define OMAP3430_ST_I2C3_MASK (1 << 17) 262 #define OMAP3430_ST_I2C2_SHIFT 16 263 #define OMAP3430_ST_I2C2_MASK (1 << 16) 264 #define OMAP3430_ST_I2C1_SHIFT 15 265 #define OMAP3430_ST_I2C1_MASK (1 << 15) 266 #define OMAP3430_ST_UART2_SHIFT 14 267 #define OMAP3430_ST_UART2_MASK (1 << 14) 268 #define OMAP3430_ST_UART1_SHIFT 13 269 #define OMAP3430_ST_UART1_MASK (1 << 13) 270 #define OMAP3430_ST_GPT11_SHIFT 12 271 #define OMAP3430_ST_GPT11_MASK (1 << 12) 272 #define OMAP3430_ST_GPT10_SHIFT 11 273 #define OMAP3430_ST_GPT10_MASK (1 << 11) 274 #define OMAP3430_ST_MCBSP5_SHIFT 10 275 #define OMAP3430_ST_MCBSP5_MASK (1 << 10) 276 #define OMAP3430_ST_MCBSP1_SHIFT 9 277 #define OMAP3430_ST_MCBSP1_MASK (1 << 9) 278 #define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5 279 #define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5) 280 #define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4 281 #define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4) 282 #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5 283 #define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5) 284 #define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4 285 #define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4) 286 #define OMAP3430_ST_D2D_SHIFT 3 287 #define OMAP3430_ST_D2D_MASK (1 << 3) 288 289 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 290 #define OMAP3430_EN_GPIO1_MASK (1 << 3) 291 #define OMAP3430_EN_GPIO1_SHIFT 3 292 #define OMAP3430_EN_GPT12_MASK (1 << 1) 293 #define OMAP3430_EN_GPT12_SHIFT 1 294 #define OMAP3430_EN_GPT1_MASK (1 << 0) 295 #define OMAP3430_EN_GPT1_SHIFT 0 296 297 /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */ 298 #define OMAP3430_EN_SR2_MASK (1 << 7) 299 #define OMAP3430_EN_SR2_SHIFT 7 300 #define OMAP3430_EN_SR1_MASK (1 << 6) 301 #define OMAP3430_EN_SR1_SHIFT 6 302 303 /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 304 #define OMAP3430_EN_GPT12_MASK (1 << 1) 305 #define OMAP3430_EN_GPT12_SHIFT 1 306 307 /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ 308 #define OMAP3430_ST_SR2_SHIFT 7 309 #define OMAP3430_ST_SR2_MASK (1 << 7) 310 #define OMAP3430_ST_SR1_SHIFT 6 311 #define OMAP3430_ST_SR1_MASK (1 << 6) 312 #define OMAP3430_ST_GPIO1_SHIFT 3 313 #define OMAP3430_ST_GPIO1_MASK (1 << 3) 314 #define OMAP3430_ST_32KSYNC_SHIFT 2 315 #define OMAP3430_ST_32KSYNC_MASK (1 << 2) 316 #define OMAP3430_ST_GPT12_SHIFT 1 317 #define OMAP3430_ST_GPT12_MASK (1 << 1) 318 #define OMAP3430_ST_GPT1_SHIFT 0 319 #define OMAP3430_ST_GPT1_MASK (1 << 0) 320 321 /* 322 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, 323 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX, 324 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits 325 */ 326 #define OMAP3430_EN_MPU_MASK (1 << 1) 327 #define OMAP3430_EN_MPU_SHIFT 1 328 329 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ 330 331 #define OMAP3630_EN_UART4_MASK (1 << 18) 332 #define OMAP3630_EN_UART4_SHIFT 18 333 #define OMAP3430_EN_GPIO6_MASK (1 << 17) 334 #define OMAP3430_EN_GPIO6_SHIFT 17 335 #define OMAP3430_EN_GPIO5_MASK (1 << 16) 336 #define OMAP3430_EN_GPIO5_SHIFT 16 337 #define OMAP3430_EN_GPIO4_MASK (1 << 15) 338 #define OMAP3430_EN_GPIO4_SHIFT 15 339 #define OMAP3430_EN_GPIO3_MASK (1 << 14) 340 #define OMAP3430_EN_GPIO3_SHIFT 14 341 #define OMAP3430_EN_GPIO2_MASK (1 << 13) 342 #define OMAP3430_EN_GPIO2_SHIFT 13 343 #define OMAP3430_EN_UART3_MASK (1 << 11) 344 #define OMAP3430_EN_UART3_SHIFT 11 345 #define OMAP3430_EN_GPT9_MASK (1 << 10) 346 #define OMAP3430_EN_GPT9_SHIFT 10 347 #define OMAP3430_EN_GPT8_MASK (1 << 9) 348 #define OMAP3430_EN_GPT8_SHIFT 9 349 #define OMAP3430_EN_GPT7_MASK (1 << 8) 350 #define OMAP3430_EN_GPT7_SHIFT 8 351 #define OMAP3430_EN_GPT6_MASK (1 << 7) 352 #define OMAP3430_EN_GPT6_SHIFT 7 353 #define OMAP3430_EN_GPT5_MASK (1 << 6) 354 #define OMAP3430_EN_GPT5_SHIFT 6 355 #define OMAP3430_EN_GPT4_MASK (1 << 5) 356 #define OMAP3430_EN_GPT4_SHIFT 5 357 #define OMAP3430_EN_GPT3_MASK (1 << 4) 358 #define OMAP3430_EN_GPT3_SHIFT 4 359 #define OMAP3430_EN_GPT2_MASK (1 << 3) 360 #define OMAP3430_EN_GPT2_SHIFT 3 361 362 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */ 363 /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits 364 * be ST_* bits instead? */ 365 #define OMAP3430_EN_MCBSP4_MASK (1 << 2) 366 #define OMAP3430_EN_MCBSP4_SHIFT 2 367 #define OMAP3430_EN_MCBSP3_MASK (1 << 1) 368 #define OMAP3430_EN_MCBSP3_SHIFT 1 369 #define OMAP3430_EN_MCBSP2_MASK (1 << 0) 370 #define OMAP3430_EN_MCBSP2_SHIFT 0 371 372 /* CM_IDLEST_PER, PM_WKST_PER shared bits */ 373 #define OMAP3630_ST_UART4_SHIFT 18 374 #define OMAP3630_ST_UART4_MASK (1 << 18) 375 #define OMAP3430_ST_GPIO6_SHIFT 17 376 #define OMAP3430_ST_GPIO6_MASK (1 << 17) 377 #define OMAP3430_ST_GPIO5_SHIFT 16 378 #define OMAP3430_ST_GPIO5_MASK (1 << 16) 379 #define OMAP3430_ST_GPIO4_SHIFT 15 380 #define OMAP3430_ST_GPIO4_MASK (1 << 15) 381 #define OMAP3430_ST_GPIO3_SHIFT 14 382 #define OMAP3430_ST_GPIO3_MASK (1 << 14) 383 #define OMAP3430_ST_GPIO2_SHIFT 13 384 #define OMAP3430_ST_GPIO2_MASK (1 << 13) 385 #define OMAP3430_ST_UART3_SHIFT 11 386 #define OMAP3430_ST_UART3_MASK (1 << 11) 387 #define OMAP3430_ST_GPT9_SHIFT 10 388 #define OMAP3430_ST_GPT9_MASK (1 << 10) 389 #define OMAP3430_ST_GPT8_SHIFT 9 390 #define OMAP3430_ST_GPT8_MASK (1 << 9) 391 #define OMAP3430_ST_GPT7_SHIFT 8 392 #define OMAP3430_ST_GPT7_MASK (1 << 8) 393 #define OMAP3430_ST_GPT6_SHIFT 7 394 #define OMAP3430_ST_GPT6_MASK (1 << 7) 395 #define OMAP3430_ST_GPT5_SHIFT 6 396 #define OMAP3430_ST_GPT5_MASK (1 << 6) 397 #define OMAP3430_ST_GPT4_SHIFT 5 398 #define OMAP3430_ST_GPT4_MASK (1 << 5) 399 #define OMAP3430_ST_GPT3_SHIFT 4 400 #define OMAP3430_ST_GPT3_MASK (1 << 4) 401 #define OMAP3430_ST_GPT2_SHIFT 3 402 #define OMAP3430_ST_GPT2_MASK (1 << 3) 403 404 /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ 405 #define OMAP3430_EN_CORE_SHIFT 0 406 #define OMAP3430_EN_CORE_MASK (1 << 0) 407 408 409 410 /* 411 * Maximum time(us) it takes to output the signal WUCLKOUT of the last 412 * pad of the I/O ring after asserting WUCLKIN high. Tero measured 413 * the actual time at 7 to 8 microseconds on OMAP3 and 2 to 4 414 * microseconds on OMAP4, so this timeout may be too high. 415 */ 416 #define MAX_IOPAD_LATCH_TIME 100 417 # ifndef __ASSEMBLER__ 418 419 /** 420 * struct omap_prcm_irq - describes a PRCM interrupt bit 421 * @name: a short name describing the interrupt type, e.g. "wkup" or "io" 422 * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs 423 * @priority: should this interrupt be handled before @priority=false IRQs? 424 * 425 * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers. 426 * On systems with multiple PRM MPU IRQ registers, the bitfields read from 427 * the registers are concatenated, so @offset could be > 31 on these systems - 428 * see omap_prm_irq_handler() for more details. I/O ring interrupts should 429 * have @priority set to true. 430 */ 431 struct omap_prcm_irq { 432 const char *name; 433 unsigned int offset; 434 bool priority; 435 }; 436 437 /** 438 * struct omap_prcm_irq_setup - PRCM interrupt controller details 439 * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register 440 * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register 441 * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers 442 * @nr_irqs: number of entries in the @irqs array 443 * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs) 444 * @irq: MPU IRQ asserted when a PRCM interrupt arrives 445 * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending 446 * @ocp_barrier: fn ptr to force buffered PRM writes to complete 447 * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs 448 * @restore_irqen: fn ptr to save and clear IRQENABLE regs 449 * @saved_mask: IRQENABLE regs are saved here during suspend 450 * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true 451 * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init 452 * @suspended: set to true after Linux suspend code has called our ->prepare() 453 * @suspend_save_flag: set to true after IRQ masks have been saved and disabled 454 * 455 * @saved_mask, @priority_mask, @base_irq, @suspended, and 456 * @suspend_save_flag are populated dynamically, and are not to be 457 * specified in static initializers. 458 */ 459 struct omap_prcm_irq_setup { 460 u16 ack; 461 u16 mask; 462 u8 nr_regs; 463 u8 nr_irqs; 464 const struct omap_prcm_irq *irqs; 465 int irq; 466 void (*read_pending_irqs)(unsigned long *events); 467 void (*ocp_barrier)(void); 468 void (*save_and_clear_irqen)(u32 *saved_mask); 469 void (*restore_irqen)(u32 *saved_mask); 470 u32 *saved_mask; 471 u32 *priority_mask; 472 int base_irq; 473 bool suspended; 474 bool suspend_save_flag; 475 }; 476 477 /* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */ 478 #define OMAP_PRCM_IRQ(_name, _offset, _priority) { \ 479 .name = _name, \ 480 .offset = _offset, \ 481 .priority = _priority \ 482 } 483 484 extern void omap_prcm_irq_cleanup(void); 485 extern int omap_prcm_register_chain_handler( 486 struct omap_prcm_irq_setup *irq_setup); 487 extern int omap_prcm_event_to_irq(const char *event); 488 extern void omap_prcm_irq_prepare(void); 489 extern void omap_prcm_irq_complete(void); 490 491 # endif 492 493 #endif 494 495