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Searched refs:OSSR (Results 1 – 5 of 5) sorted by relevance

/arch/arm/mach-sa1100/
Dtime.c36 writel_relaxed(OSSR_M0, OSSR); in sa1100_ost0_interrupt()
63 writel_relaxed(OSSR_M0, OSSR); in sa1100_osmr0_set_mode()
86 writel_relaxed(0x0f, OSSR); in sa1100_timer_resume()
123 writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR); in sa1100_timer_init()
/arch/arm/mach-pxa/
Dtime.c51 writel_relaxed(OSSR_M0, OSSR); in pxa_ost0_interrupt()
76 writel_relaxed(OSSR_M0, OSSR); in pxa_osmr0_set_mode()
83 writel_relaxed(OSSR_M0, OSSR); in pxa_osmr0_set_mode()
150 writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR); in pxa_timer_init()
Dreset.c81 writel_relaxed(OSSR_M3, OSSR); in do_hw_reset()
/arch/arm/mach-pxa/include/mach/
Dregs-ost.h18 #define OSSR io_p2v(0x40A00014) /* OS Timer Status Register */ macro
/arch/arm/mach-sa1100/include/mach/
DSA-1100.h838 #define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */ macro